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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 21/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
11
Lucent Technologies Inc.
List of Tables
(continued)
Table
Page
Table 145. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18)
((671—672); (C71—C72)) ..................................................................................................................187
Table 146. Automatic AIS to the System and Automatic Loopback Enable Register
(FRM_PR19) (673; C73).....................................................................................................................188
Table 147. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74).....................................188
Table 148. Framer FDL Control Command Register (FRM_PR21) (675; C75) ....................................................189
Table 149. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76)...................................................189
Table 150. Framer System Stuffed Time Slot Code Register (FRM_PR23) (677; C77).......................................189
Table 151. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78)..........................................190
Table 152. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 ..........................................................190
Table 153. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79) .....................................191
Table 154. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 ..........................................................191
Table 155. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A).............................192
Table 156. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1
Control Register (FRM_PR27) (67B, C7B).........................................................................................193
Table 157. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C)....................194
Table 158. Sa4—Sa8 Source Register (FRM_PR29) (67D; C7D)........................................................................195
Table 159. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29........................................................................195
Table 160. Sa4—Sa8 Control Register (FRM_PR30) (67E; C7E)........................................................................196
Table 161. Sa Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88)) .......................................197
Table 162.
SLC
-96 Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88))................................197
Table 163. Transmit
SLC
-96 FDL Format.............................................................................................................197
Table 164. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register
(FRM_PR41) (689; C89).....................................................................................................................198
Table 165. Framer Exercise Register (FRM_PR42) (68A; C8A) ..........................................................................198
Table 166. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A) .....................................................................199
Table 167. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B)...201
Table 168. Signaling Mode Register (FRM_PR44) (68C; C8C)............................................................................202
Table 169. CHI Common Control Register (FRM_PR45) (68D; C8D)..................................................................203
Table 170. CHI Common Control Register (FRM_PR46) (68E; C8E) ..................................................................204
Table 171. CHI Transmit Control Register (FRM_PR47) (68F; C8F) ...................................................................205
Table 172. CHI Receive Control Register (FRM_PR48) (690; C90).....................................................................205
Table 173. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) ((691—694); (C91—C94)) ...206
Table 174. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) ((695—698); (C95—C98)) ....206
Table 175. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) ((699—69C); (C99—C9C)).....206
Table 176. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) ((69D—6A0); (C9D—CA0)).....207
Table 177. CHI Transmit Control Register (FRM_PR65) (6A1; CA1)...................................................................207
Table 178. CHI Receive Control Register (FRM_PR66) (6A2; CA2)....................................................................207
Table 179. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5).............................................208
Table 180. Pattern Detector Control Register (FRM_PR70) (6A6; CA6)..............................................................209
Table 181. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23)
((6E0—6F7); (CE0—CF7)) .................................................................................................................210
Table 182. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31)
((6E0—6FF); (CE0—CFF)).................................................................................................................210
Table 183. FDL Register Set (800—80E); (E00—E0E)........................................................................................211
Table 184. FDL Configuration Control Register (FDL_PR0) (800; E00)...............................................................212
Table 185. FDL Control Register (FDL_PR1) (801; E01) .....................................................................................212
Table 186. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02) .............................................................213
Table 187. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03)............................................214
Table 188. FDL Transmitter FIFO Register (FDL_PR4) (804; E04)......................................................................214
Table 189. FDL Transmitter Mask Register (FDL_PR5) (805; E05) .....................................................................214
Table 190. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06) ..............................................215
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