- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299156 > GE28F640W30TD70 (INTEL CORP) 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 PDF資料下載
參數(shù)資料
| 型號(hào)： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數(shù)： | 91/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁當(dāng)前第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
28F640W30, 28F320W30, 28F128W30
Datasheet
Intel Wireless Flash Memory (W30)
June 2005
Order Number: 290702, Revision: 011
87
14.6
WAIT Delay (RCR[8])
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. This bit setting depends on the system and CPU characteristics. The WAIT can
be asserted either during, or one data cycle before, a valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-word, 8-word, 16-word, or
continuous-word burst mode, an output delay might occur when a burst sequence crosses its first
flash device-row boundary (16-word boundary).
If the burst start address is 4-word boundary aligned, the delay does not occur.
If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode
read sequence. The WAIT signal informs the system of this delay.
14.7
Burst Sequence (RCR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 30, “Sequence and
Burst Length” on page 88). When operating in a linear burst mode, either 4-word, 8-word, or
16-word burst length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the flash
device might incur an output delay when the burst sequence crosses the first 16-word boundary.
(See Figure 39, “Word Boundary” on page 84 for word boundary description.)
Whether this delay occurs depends on the starting address.
If the starting address is aligned to a 4-word boundary, there is no delay.
If the starting address is the end of a 4-word boundary, the output delay is one clock cycle less
than the First Access Latency Count; this is the worst-case delay.
The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. The
WAIT pin informs the system of this delay. For timing diagrams of WAIT functionality, see these
figures:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GEN12.5-120 | Programmable DC Power Supplies 750W/1500W |
| GEN12.5-60 | Programmable DC Power Supplies 750W/1500W |
| GFL750 | COPPER ALLOY, WIRE TERMINAL |
| GFL500 | COPPER ALLOY, WIRE TERMINAL |
| GFL350 | COPPER ALLOY, WIRE TERMINAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GE28F800B3BA90 | 制造商:Intel 功能描述:NOR Flash, 512K x 16, 45 Pin, Plastic, BGA |
| GE28F800B3TA90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Advanced Boot Block Flash Memory |
| GE28F800C3BA70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3) |
| GE28F800C3BA90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3) |
| GE28F800C3BC70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。