參數(shù)資料
型號(hào)： GE28F640W30TD70
廠商： INTEL CORP
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56
封裝： 0.75 MM PITCH, VFBGA-56
文件頁(yè)數(shù)： 19/104頁(yè)
文件大?。?/td> 1443K
代理商： GE28F640W30TD70
28F640W30, 28F320W30, 28F128W30
Datasheet
Intel Wireless Flash Memory (W30)
June 2005
Order Number: 290702, Revision: 011
21
4.2
Signal Descriptions
Table 5 describes the signals for the 56-ball VF BGA and BGA Chip Scale Package.
Table 6 describes the signals for the QUAD+ package ballout.
Table 5.
Signal Descriptions - BGA Package & VF BGA Package (Sheet 1 of 2)
Symbol
Type
Name and Function
A[22:0]
Input
ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
D[15:0]
Input/
Output
DATA INPUTS/OUTPUTS:
Inputs data and commands during write cycles.
Outputs data during reads.
Data pins are High-Z when the flash device or its outputs are deselected. Data is internally latched
during writes.
ADV#
Input
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on the rising edge of ADV#, or the next valid CLK edge with
ADV# low, whichever occurs first.
CE#
Input
CHIP ENABLE:
Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the flash device, places it in standby mode, and tri-states all outputs.
CLK
Input
CLOCK: CLK synchronizes the flash device to the system bus frequency during synchronous reads
and increments an internal address generator. During synchronous read operations, addresses are
latched on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
OE#
Input
OUTPUT ENABLE:
When asserted, OE# enables the flash device output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RST#
Input
RESET: When low, RST# resets internal automation and inhibits write operations. This reset provides
data protection during power transitions. De-asserting RST# enables normal operation and places the
flash device in asynchronous read-array mode.
WAIT
Output
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be
asserted-high or asserted-low, based on bit 10 of the Read Configuration Register. WAIT is tri-stated if
CE# is deasserted. WAIT is not gated by OE#.
WE#
Input
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
WP#
Input
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
VPP
Power/
Input
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Flash
memory contents cannot be altered when VPP < VPPLK. Do not attempt block erase and program
operations at invalid VPP voltages.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash device modification. VPP can be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V might reduce block cycling capability.
VCC
Power
FLASH DEVICE POWER SUPPLY: Writes are inhibited at VCC < VLKO. Do not attempt flash device
operations at invalid VCC voltages.
VCCQ
Power
OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ.
VSS
Power
GROUND: Pins for all internal flash device circuitry must be connected to system ground.
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