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參數(shù)資料
| 型號(hào)： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數(shù)： | 89/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
Datasheet
Intel Wireless Flash Memory (W30)
June 2005
Order Number: 290702, Revision: 011
85
14.3
WAIT Signal Polarity (RCR[10])
If the WT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. A 0 on the
WAIT signal indicates that data is not ready and the data bus contains invalid data.
Conversely, if RCR[10] is set, then WAIT is asserted high.
In either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during
asynchronous page mode reads.
14.4
WAIT Signal Function
The WAIT signal indicates data valid when the flash device is operating in synchronous mode
(RCR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT
signal is deasserted only when data is valid on the bus.
When the flash device is operating in synchronous non-read-array mode, such as read status,
read ID, or read query, WAIT is set to an asserted state, as determined by RCR[10]. See Figure
When the flash device is operating in asynchronous page mode or asynchronous single word
read mode, WAIT is set to an asserted state, as determined by RCR[10]. See Figure 10, “Page-
From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the
flash device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or
Read Status), or if the flash device is operating in asynchronous mode (RCR[15]=1). In these cases,
the system software must ignore (mask) the WAIT signal, because WAIT does not convey any
useful information about the validity of what is appearing on the data bus.
CONDITION
WAIT
CE# = VIH
CE# = VIL
Tri-State
Active
OE#
No-Effect
Synchronous Array Read
Active
Synchronous Non-Array Read
Asserted
All Asynchronous Read and all Write
Asserted
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