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參數資料
| 型號： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數： | 53/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
52
Order Number: 290702, Revision: 011
9.1.4
Reset
The flash device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is
turned off and outputs are placed in a high-impedance state.
After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is
required before a write sequence can be initiated. After this wake-up interval, normal operation is
restored. The flash device defaults to read-array mode, the status register is set to 80h, and the Read
Configuration Register defaults to asynchronous page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the memory
contents at the aborted block or address are invalid. See Figure 21, “Reset Operations Waveforms”
on page 47 for detailed information regarding reset timings.
As on any automated device, RST# must be asserted during system reset. When the system comes
out of reset, the processor expects to read from the flash memory array. Automated flash memory
devices provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, the CPU might not be properly initialized, because the flash
memory device might be providing status information instead of array data. 1.8 Volt Intel Flash
memory devices allow proper CPU initialization following a system reset through the use of the
RST# input. In this application, RST# is controlled by the same CPU reset signal, RESET#.
9.1.5
Write
A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash memory control
commands are written to the CUI using standard microprocessor write timings. Proper use of the
ADV# input is needed for proper latching of the addresses. Refer to Section 7.3, “AC Write
Characteristics” on page 40 for details. The address and data are latched on the rising edge of WE#.
Write operations are asynchronous; CLK is ignored (but can be kept active/toggling).
The CUI does not occupy an addressable memory location within any partition. The system
processor must access it at the correct address range, depending on the kind of command executed.
Programming or erasing can occur in only one partition at a time. Other partitions must be in one of
the read modes or erase suspend mode.
Table 18, “Command Codes and Descriptions” on page 53 shows the available commands.
Appendix A, “Write State Machine” on page 90 provides information about moving between
different operating modes using CUI commands.
9.2
Flash Device Commands
The flash device on-chip WSM manages erase and program algorithms. This local CPU (WSM)
controls the flash device in-system read, program, and erase operations. Bus cycles to or from the
flash memory device conform to standard microprocessor bus cycles. The RST#, CE#, OE#, WE#,
and ADV# control signals dictate data flow into and out of the flash device. WAIT informs the
CPU of valid data during burst reads. Table 17, “Bus Operations Summary” on page 50
summarizes bus operations.
To select flash device operations, write specific commands into the flash device CUI. Table 18,
“Command Codes and Descriptions” on page 53 lists all possible command codes and
descriptions. Table 19, “Bus Cycle Definitions” on page 55 lists command definitions. Because
commands are partition-specific, you must issue write commands within the target address range.
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