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參數(shù)資料
| 型號(hào)： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數(shù)： | 21/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
Datasheet
Intel Wireless Flash Memory (W30)
June 2005
Order Number: 290702, Revision: 011
23
F[2:1]-OE#
Input
FLASH OUTPUT ENABLE: Low-true input.
Fx-OE# low enables the output buffers on the selected flash memory device.
F[2:1]-OE# high disables the output buffers on the selected flash memory device, placing them in
High-Z.
F1-OE# controls the outputs of flash die #1.
F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked
combinations with two or three flash die, and is RFU on stacked combinations with only one flash
die.
R-OE#
Input
RAM OUTPUT ENABLE: Low-true input.
R-OE# low enables the output buffers on the selected RAM.
R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z.
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
F-WE#
Input
FLASH WRITE ENABLE: Low-true input.
F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of
F-WE#.
R-WE#
Input
RAM WRITE ENABLE: Low-true input.
R-WE# controls writes to the selected RAM die.
R-WE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
CLK
Input
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and
increments the internal address generator.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
During asynchronous mode read operations, addresses are latched on the rising edge ADV#, or
are continuously flow-through when ADV# is kept asserted.
WAIT
Output
WAIT: Output signal.
Indicates invalid data during synchronous array or non-array flash memory reads. Read Configuration
Register bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is
deasserted; WAIT is not gated by F-OE#.
In synchronous array or non-array flash memory read modes, WAIT indicates invalid data when
asserted and valid data when deasserted.
In asynchronous flash memory page read, and all flash memory write modes, WAIT is asserted.
F-WP#
Input
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash die.
F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked
using software commands.
F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked
using software commands.
ADV#
Input
ADDRESS VALID: Low-true input.
During synchronous flash memory read operations, addresses are latched on the rising edge of
ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
During asynchronous flash memory read operations, addresses are latched on the rising edge of
ADV#, or are continuously flow-through when ADV# is kept asserted.
Table 6.
Signal Descriptions - QUAD+ Package (Sheet 2 of 3)
Symbol
Type
Description
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