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參數(shù)資料
| 型號： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數(shù)： | 46/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
46
Order Number: 290702, Revision: 011
8.4
Power-Up/Down Characteristics
The flash device is protected against accidental block erasure or programming during power
transitions. Power supply sequencing is not required if VCC and VPP are connected together; so it
does not matter whether VPP or VCC powers-up first. If VPP is not connected to the system supply,
then VCC must attain VCCMIN before applying VCCQ and VPP. Do not drive flash device inputs
before supply voltage = VCCQMIN. Power supply transitions can occur only when RST# is low.
8.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase flash devices,
because the system expects to read from the flash memory when it comes out of reset. If a CPU
reset occurs without a flash memory reset, the CPU is not properly initialized, because the flash
memory might be providing status information instead of array data.
Note:
To allow proper CPU/flash device initialization at system reset, connect RST# to the system CPU
RESET# signal.
System designers must guard against spurious writes when VCC voltages are above VLKO.
Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits
writes to the flash device. The CUI architecture provides additional protection, because memory
contents can be altered only after successful completion of the two-step command sequences.
The flash device is also disabled until RST# is brought to VIH, regardless of its control input states.
By holding the flash device in reset (RST# connected to system PowerGood) during power-up/
down, invalid bus conditions during power-up can be masked, providing yet another level of
memory protection.
8.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software, and is not altered by VPP or CE#
transitions or WSM actions. Read-array mode is the power-up default state after the flash device
exits from reset mode or after VCC transitions above VLKO (Lockout voltage).
After completing program or block erase operations (even after VPP transitions below VPPLK), the
Read Array command must reset the CUI to read-array mode if flash memory array access is
desired.
8.5
Power Supply Decoupling
When the flash device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and switch voltages. This internal activity produces transient noise.
To minimize the effect of this transient noise, device decoupling capacitors are required. Transient
current magnitudes depend on the flash device output capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection suppresses these transient voltage peaks.
Note:
Each flash device must have a 0.1 F ceramic capacitor connected between each power (VCC,
VCCQ, VPP), and ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance
capacitors must be as close as possible to the package signals.
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