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參數(shù)資料
| 型號(hào)： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁(yè)數(shù)： | 57/104頁(yè) |
| 文件大小： | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
56
Order Number: 290702, Revision: 011
9.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation can occur between the
two write cycles. The setup phase of a 2-cycle write sequence places the addressed partition into
read-status mode, so if the same partition is read before the second confirm write cycle is issued,
status register data is returned. Reads from other partitions, however, can return actual array data, if
conditions.
By contrast, a write bus cycle must not interrupt a 2-cycle write sequence. Such an interruption
causes a command sequence error to appear in the status register. Figure 27 illustrates a command
sequence error.
Figure 25.
Normal Write and Read Cycles
Figure 26.
Interleaving a 2-Cycle Write Sequence with an Array Read
Partition A
20h
D0h
FFh
Block Erase Setup
Block Erase Conf irm
Read Array
Address [A]
WE# [W]
OE# [G]
Data [Q]
Partition B
Partition A
Partition B
Partition A
FFh
20h
Array Data
D0h
Read Array
Erase Set up
Bus Read
Erase Conf irm
Address [A]
WE# [W]
OE# [G]
Data [Q]
Figure 27.
Improper Command Sequencing
Parti tion X
Parti tio n Y
Parti tion X
Partition X
20h
FFh
D0h
SR Data
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
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