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參數(shù)資料
| 型號(hào)： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數(shù)： | 73/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
70
Order Number: 290702, Revision: 011
12.2
Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm
(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode
at a time; other partitions must be in a read mode. The Erase Confirm command internally latches
the address of the block to erase. Erase forces all bits within the block to 1.
SR[7] is cleared while the erase executes.
After writing the Erase Confirm command, the selected partition is placed in read status register
mode. Reads performed to that partition return the current status data. The address given during the
Erase Confirm command does not need to be the same address used in the Erase Setup command.
For example, if the Erase Confirm command is given to partition B, then the selected block in
partition B is erased, even if the Erase Setup command was to partition A.
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, to
execute properly, an Erase Setup command must be immediately followed by the Erase Confirm
command. If a different command is issued between the setup and confirm commands, the
following occurs:
The partition is placed in read-status mode.
The status register signals a command sequence error.
All subsequent erase commands to that partition are ignored until the status register is cleared.
To detect block erase completion, the CPU analyzes SR[7] of that partition. If an error bit
(SR[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition remains in read-status mode until
another command is written to its CUI. Any CUI instruction can follow after erasing completes.
The CUI can be set to read-array mode to prevent inadvertent status register reads.
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