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參數(shù)資料
| 型號： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數(shù)： | 86/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
82
Order Number: 290702, Revision: 011
Table 28.
Read Configuration Register Descriptions
Bit
Name
Description1
Notes
15
RM
Read Mode
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
14
R
Reserved
13-11
LC[2:0]
First Access Latency
Count
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
6
10
WP
WAIT Signal Polarity
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
9
DOC
Data Output Configuration
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
6
8
WC
WAIT Configuration
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
6
7
BS
Burst Sequence
1 = Linear Burst Order (Default)
6
CC
Clock
Configuration
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
5
R
Reserved
4
R
Reserved
3
BW
Burst Wrap
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
2-0
BL[2:0]
Burst Length
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16-Word Burst (Available on the 130 nm lithography)
111 = Continuous Burst (Default)
Notes:
1.
Undocumented combinations of bits are reserved by Intel for future implementations.
2.
Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register
and configuration reads support single read cycles. RCR[15]=1 disables the configuration set by RCR[14:0].
3.
Data is not ready when WAIT is asserted.
4.
Set the synchronous burst length. In asynchronous page mode, the burst length equals four words.
5.
Set all reserved Read Configuration Register bits to zero.
6.
Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data
hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported.
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