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CHAPTER 4 INTERFACES
81
Whether to enable fast back-to-back transactions is set in the BBL field of the GMR register. As many fast
back-to-back transactions as the number set in the BBL field are enabled. The maximum count is 7. The
following table lists each setting of the BBL field and the corresponding fast back-to-back transaction count.
BBL field
Fast back-to-back transaction count
000
Disabled.
001
Disabled.
010
2
011
3
100
4
101
5
110
6
111
7
Default = 000: Disabled.
When the setting in the BBL field enables fast back-to-back transactions, the
μ
PD98405 attempts to
execute master transactions in fast back-to-back mode whenever the target responds to a fast back-to-
back transaction.
(3) 64-bit bus expansion
The
μ
PD98405 supports 64-bit bus expansion (64-bit data transfer and 64-bit addressing).
When using 64-bit data transfer, set the E64 bit of the GMR register to 1. When the E64 bit is set to 1, the
μ
PD98405 requests 64-bit data transfer, and the target executes 64-bit data transfer in response. When
the target fails to respond to the request (when ACK64_B is not set to active low), 32-bit data transfer is
performed.
When using 64-bit addressing (DAC command), set the value of the high-order 32 bits of the 64-bit address
in the PBAH register. The
μ
PD98405 executes 64-bit addressing using the high-order 32-bit addresses set
in the PBAH register. When 0 is set in the PBAH register, the
μ
PD98405 executes 32-bit addressing.
The 64-bit bus expansion function is supported only when the
μ
PD98405 is being used as a master. When
the
μ
PD98405 is acting as a target, the 32-bit bus function is used.
The following figure shows the 64-bit bus transaction timing.