![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_313.png)
CHAPTER 7 REGISTERS
313
(10) MAU (MAC address upper 32 bits)
Address:
307H
Access mode: Read/write
MAL (MAC address lower 16 bits)
Address:
308H
Access mode: Read/write
The MAU and MAL registers are set when performing MAC address filtering, one of the LAN emulation
functions of the
μ
PD98405. The
μ
PD98405 performs filtering using the 48-bit MAC address set in the MAU
and MAL registers. For the host, set its own 48-bit MAC address (UNI cast address) in the MAU and MAL
registers. The
μ
PD98405 discards those received packets whose destination addresses do not match the
48-bit MAC address set in the MAU and MAL registers. The default values of these registers will be 0 after
a reset. For details, see
Section
5.7
. It is not possible to write to bits 31 to 16 of the MAL register. Upon a
read, 0 is returned.
31
0
31
0
MAL
MAU
0
Address
Address
16
15
(11) APR (ABR parameter register)
Address:
400H
Access mode: Read/write
The APR register is used to set the parameters for each of the ABR service ports. The parameters set for
each channel (VC) are set in the transmission/reception VC table. It is not possible to write to bits 7 and 6.
Upon a read, 0 is returned.
31
0
CRM
- 0 -
16
15
Trm0
7
Nrm0
Mrm
3
2
5
6
8
Trm0
The Trm parameter is used to set the time required to transmit the FRM cell required by the active
source.
The host must set Trm0 so that Trm is expressed in cell time units. (1 cell time = 2.8312
μ
s. The
μ
PD98405 performs rate calculation by excluding the overhead incurred by SONET/SDH, giving a
maximum rate of 149.76 Mbps).
Trm (milliseconds) = Trm0*2.8312/1000
Default value after reset (Trm0): 35,321 (89F9H)