![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_320.png)
CHAPTER 7 REGISTERS
320
Cautions 1. The variables and flags used by the
μ
PD98405 must be cleared to 0 and the
parameters (I, M, P, C, and Priority) must be set before the enable bit (E) of a
scheduler register can be set to 1.
2. All the variables and flags in the scheduler registers of a shaper must be cleared to 0
before operation of the shaper can start.
3. The contents of the scheduler registers cannot be changed while the A bit is set to 1,
that is, while the corresponding shaper is active. A shaper is inactive while no VC
table is linked to it. Before attempting to change the I, M, P, or C parameter, ensure
that the shaper is inactive (A bit = 0) then clear its enable bit (E) to 0. In such a case,
all the variables and flags used by the
μ
PD98405 must also be cleared to 0.
4. The host can modify the value of the priority parameter, but no other parameters, at
any time. Furthermore, modification is also possible while the shaper is active (A bit
= 1). In this case, set only the byte enable B3 bit of the Indirect_Access command to
1 to ensure that all other fields are not overwritten.
Address (H)
0 - F
10 - 1F
20 - 2F
30 - 3F
Register
I, M
x
y
P, C, p, c
Access mode
Read/write
Read/write
Read/write
Read/write
Function
I and M parameters of schedulers 0 through 15
x value of schedulers 0 through 15
y value of schedulers 0 through 15
P and C parameters and p and c values of schedulers 0
through 15
Priority and status of schedulers 0 through 15
Priority of ABR scheduler (in-rate)
Priority of ABR scheduler (out-of-rate)
40 - 4F
50
51
Pri & Status
Priority
Priority
Read/write
Read/write
Read/write
31
0
31
0
31
0
31
0
16
15
24
23
31
0
27
26
5
- 0 -
24
23
2
1
4
3
M
Pri & Status
register
P, C, p, c
register
y
register
x
register
I, M
register
I
x
y
P
C
8
7
p
c
PRIORITY
S
R
AGM
A
E