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CHAPTER 6 PHY FUNCTION
279
Figure 6-8. Counter-Related Registers (Example: HEC Error Counter)
Window register:
HECCT
HECC[1:0] = 10
HECC[1:0] = 01
HECC[1:0] = 00
23
19
16 15
8
7
0
Load register:
HECCNTR
0
0
0
0
Load by SMP bit = 1
19
16 15
8
7
0
Counter:
HEC
counter
The counter also has the following functions:
(1) Clearing all counters
By setting the PCR bit of command register 2 (PCMR2) to "1", all the counters can be cleared to 0. The
PCR bit is automatically reset to 0 after the counters have been cleared.
(2) Clearing each counter
When the bit of the PCIR1 and PCIR2 registers corresponding to the counter to be cleared is set to "1",
only the corresponding counter is cleared to 0. The set bit is automatically reset to 0 after the counter
has been cleared.
(3) Loading all counters
When the SMP bit of the PCSR register is set to "1", the current values of all the counters are stored
into the corresponding load registers. The SMP bit is reset to 0 after the counter values have been
stored into the load registers.
(4) Stopping an unused counter
To reduce the power consumption, unused counters can be stopped. When the bit of the PCFR1 and
PCFR2 registers corresponding to a counter that is not to be used is set to 1, that counter is stopped.
(5) Reporting overflow of each counter
If the count value exceeds all "F", the
μ
PD98405 sets the corresponding bit of the PCOCR1 and
PCOCR2 registers to "1", reporting the occurrence of an overflow by using an interrupt. The interrupt
can be masked bitwise.