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CHAPTER 7 REGISTERS
344
(23) Information cell count register (INFCT)
7
0
Address
Default
R/W
INFCT
16H
00H
R
INFC[1:0] = 10
INFC[1:0] = 01
INFC[1:0] = 00
23
19
16 15
8
7
0
INFCNTR
0
0
0
0
The SMP bit is set to 1
19
16 15
8
7
0
Information cell counter
This is a window register that is used to read the contents of the 20-bit
INFCNTR
register by reading eight
bits, eight bits, and four bits, three times. First, the low-order eight bits (
INFCNTR[7:0]
) are read, then the
middle eight bits (
INFCNTR[15:8]
), and finally the high-order four bits (
INFCNTR[19:16]
). Which of the
low-order, middle, or high-order bits is read is indicated by the
INFC1
and
INFC0
bits of the
PCPR2
register (address: 1AH). For each of these bits, the default value is 00. Each time the
INFCT
register is
read, the value of these bits is automatically changed in the order of 00 -> 01 -> 10 -> 00 -> 01.
INFCNTR
is a load register that is used to sample (store) the value of the information cell counter. By
setting the
SMP
bit of the
PCSR
register (address: 1BH) to 1, the value of the
information cell counter
is
stored into the
INFCNTR
register. This value indicates the number of valid cells that have been received
(cells that have been transferred to the ATM layer device) since the contents of the
information cell
counter
were last sampled. The value stored into the
INFCNTR
register is held until the
information cell
counter
is next sampled.
Sampling the contents of the
information cell counter
causes the counter to be cleared to 0. The counter
is also cleared to 0 when the
INFC
bit of the
PCIR2
register (address: 1DH) is set to 1.
When the value of the counter is all F, the
INFC
bit of the
PCOCR2
register (address: 21H) is set to 1 to
indicate a counter overflow being detected. Also, the
PCO
bit of the
PICR
register (address: 06H) is set to
1, thus causing an interrupt. After the occurrence of an overflow, the
information cell counter
again
starts to count up from 0.