![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_149.png)
CHAPTER 5 SAR FUNCTION
149
Idle cell
Header = all 00s in hex except for CLP = 1; payload = all 6As in hex
Header
Payload
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
...
Byte 47 Byte 48
Content
00
00
00
01
00
6A
6A
...
6A
6A
(b) Mode in which neither an unassigned nor idle cell is transmitted for rate adjustment
The
μ
PD98405 can select a mode in which neither an unassigned nor idle cell is transmitted for rate
adjustment. In this mode, neither an unassigned nor idle cell is output at any time. The
μ
PD98405
transmits data cells (including RM and OAM cells) only. This mode can be selected using the UID bit of
the GMR register.
Mode in which a cell is not transmitted for rate adjustment
0
A rate adjustment cell is inserted.
1
No rate adjustment cell is inserted.
UID bit
(Bit 29 of the GMR)
Default setting = 0
In the mode in which a rate adjustment cell is not transmitted, if there is no data cell to be transmitted,
the
μ
PD98405 deactivates the TENBL_B signal to disable cell transmission. If no cell is transmitted, it is
impossible for the built-in PHY layer and ATM PHY layer chips to adjust the timing to maintain the
transmission rate. This mode is useful, therefore, in those cases in which no built-in or ATM PHY layer
is used.
It is also impossible to use the unassigned/idle cell generator in the mode in which a rate adjustment cell
is not transmitted.
(4) Scheduler register
Each of the 16 shapers has a scheduler register that stores the parameters set by the host, as well as the
variables managed by the
μ
PD98405. For details, see
Section 7.3 (20)
.
The user sets the following parameters in the scheduler register of each shaper to be used, to determine
the rate before starting transmission. The scheduler register is an indirect address register, such that the
host can read/write the scheduler register by using the Indirect_Access command.
Remark
For details of the ABR scheduler setting, see
Section 5.8.5
.