![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_75.png)
CHAPTER 4 INTERFACES
75
Table 4-6. Configuration Register
(1/2)
Offset
Name
Bit(s)
R/W
Default
Description
Device ID
31 - 16
R
001DH
μ
PD98405 device ID
00H
Vendor ID
15 - 0
R
1033H
NEC vendor ID
31
R/W
0
Detected Parity Error
30
R/W
0
Signaled System Error
29
R/W
0
Received Master Abort.
28
R/W
0
Received Target Abort.
27
R/W
0
Signaled Target Abort.
26 - 25
R
01
DEVSEL_B timing. The
μ
PD98405 supports Medium.
24
R/W
0
Data Parity Error Reported.
23
R
1
Fast Back-to-Back Capable.
Status
22 - 16
R
00H
Reserved
15 - 10
R
00H
Reserved
9
R
0
Fast Back-to-Back Enable
8
R/W
0
System Error Enable
7
R
0
Wait Cycle Enable.
6
R/W
0
Parity Error Response
5
R
0
VGA Palette Snoop Enable.
4
R/W
0
Memory Write and Invalidate Enable.
3
R
0
Special Cycle Recognition.
2
R/W
0
Bus Master Enable.
1
R/W
0
Memory Access Enable
04H
Command
0
R/W
0
I/O Access Enable
31 - 24
R
02
Basic class: Network controller
23 - 16
R
03
Subclass: ATM controller
Class Code
15 - 8
R
00
Programming interface
08H
Revision ID
7 - 0
R
00H
Contains device revision information.
BIST
31 - 24
R
00H
Used to control the built-in self test and indicates its status.
Header Type
23 - 16
R
00H
Configuration space header type
Latency Timer
15 - 8
R/W
00H
Contains the master latency timer value for the PCI bus
master.
0CH
Cache Line Size
7 - 0
R/W
00H
Specifies the system cache line size in word (32-bit) units.
31 - 8
R/W
00H
Base address. 256-byte support.
7 - 1
R
00H
Reserved
10H
IO Base Address
0
R
1
IO space indicator
31 - 12
R/W
00H
Base address. 4K-byte support.
11 - 4
R
0H
Reserved
3
R
0
Prefetch (disable)
2 - 1
R
00
Type (the base address can be mapped onto any 32-bit
boundary.)
14H
Memory
Base Address
0
R
0
Memory Space Indicator