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CHAPTER 7 REGISTERS
338
(17) Line FEBE error count register (LFBCT)
7
0
Address
Default
R/W
LFBCT
10H
00H
R
LFBC[1:0] = 10
LFBC[1:0] = 01
LFBC[1:0] = 00
23
19
16 15
8
7
0
LFBCNTR
0
0
0
0
The SMP bit is set to 1
19
16 15
8
7
0
L-FEBE counter
This is a window register that is used to read the contents of the 20-bit
LFBCNTR
register by reading eight
bits, eight bits, and four bits, three times. First, the low-order eight bits (
LFBCNTR[7:0]
) are read, then the
middle eight bits (
LFBCNTR[15:8]
), and finally the high-order four bits (
LFBCNTR[19:16]
). Which of the
low-order, middle, or high-order bits is read is indicated by the
LFBC1
and
LFBC0
bits of the
PCPR1
register (address: 19H). For each of these bits, the default value is 00. Each time the
LFBCT
register is
read, the value of these bits is automatically changed in the order of 00 -> 01 -> 10 -> 00 -> 01.
LFBCNTR
is a load register that is used to sample (store) the value of the
L-FEBE counter
. By setting
the
SMP
bit of the
PCSR
register (address: 1BH) to 1, the value of the
L-FEBE counter
is stored into the
LFBCNTR
register. This value indicates the number of times
Line-FEBE
has been detected since the
contents of the
L-FEBE counter
were last sampled. The value stored into the
LFBCNTR
register is held
until the
L-FEBE counter
is next sampled.
Sampling the contents of the
L-FEBE counter
causes the counter to be cleared to 0. The counter is also
cleared to 0 when the
LFBC
bit of the
PCIR1
register (address: 1CH) is set to 1.
When the value of the counter is all F, the
LFBC
bit of the
PCOCR1
register (address: 20H) is set to 1 to
indicate a counter overflow being detected. Also, the
PCO
bit of the
PICR
register (address: 06H) is set to
1, thus causing an interrupt. After the occurrence of an overflow, the
L-FEBE counter
again starts to
count up from 0.