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CHAPTER 7 REGISTERS
337
(16) B3 error count register (B3ECT)
7
0
Address
Default
R/W
B3ECT
0FH
00H
R
B3EC = 1
B3EC = 0
15
8
7
0
B3ECNTR
The SMP bit is set to 1
15
8
7
0
B3E counter
This is a window register that is used to read the contents of the 16-bit
B3ECNTR
register by repeatedly
reading eight bits, two times. First, the low-order eight bits (
B3ECNTR[7:0]
) are read, followed by the
high-order eight bits (
B3ECNTR[15:8]
). Whether the low- or high-order bits are read is indicated by the
B3EC
bit of the
PCPR1
register (address: 19H). The default value of the
B3EC
bit of the
PCPR1
register
is 0. Each time the
B3ECT
register is read, the value of this bit changes in the order of 0
-> 1 -> 0.
B3ECNTR
is a load register that is used to sample (store) the value of the B3 error counter. By setting the
SMP
bit of the
PCSR
register (address: 1BH) to 1, the value of the
B3E counter
is stored into the
B3ECNTR
register. This value indicates the number of B3 errors that have occurred since the contents of
the
B3E counter
were last sampled. The value stored into the
B3ECNTR
register is held until the
B3E
counter
is next sampled.
Sampling the contents of the
B3E counter
causes the counter to be cleared to 0. The counter is also
cleared to 0 when the
B3EC
bit of the
PCIR1
register (address: 1CH) is set to 1.
When the value of the counter is all F, the
B3EC
bit of the
PCOCR1
register (address: 20H) is set to 1 to
indicate a counter overflow being detected. Also, the
PCO
bit of the
PICR
register (address: 06H) is set to
1, thus causing an interrupt. After the occurrence of an overflow, the
B3E counter
again starts to count up
from 0.