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CHAPTER 2 PIN FUNCTIONS
31
(2/4)
Symbol
Pin No.
I/O
I/O level
Function
SIZE2
SIZE1
SIZE0
63
64
65
O
TTL
Burst Size
The SIZE2 to SIZE0 signals indicate the size of the current
DMA transfer. These pins are provided to support interface
to buses that require an explicit burst size (e.g., S bus).
SIZE2
0
0
0
0
1
1
Others
SIZE1
0
0
1
1
0
0
SIZE0
0
1
0
1
0
1
Function
One-word transfer
Two-word burst
Four-word burst
Eight-word burst
Sixteen-word burst
Twelve-word burst
Undefined
DR/W_B
60
O
TTL
DMA Read/Write
The DR/W_B signal determines the direction of DMA
access.
1:
Read access
0:
Write access
Attention (DMA request)
The
μ
PD98405 sets the ATTN_B signal to low when
attempting to start DMA operation. Once only one word
remains to be transferred, the ATTN_B signal becomes
inactive at the rising edge of CLK.
Grant
Set the GNT_B signal to low once the bus arbiter has
granted bus mastership in response to a DMA request from
the
μ
PD98405. By detecting the GNT_B signal being set to
active low, the
μ
PD98405 assumes that bus mastership has
been granted and starts DMA operation.
Target Device Ready
RDY_B is used in DMA cycles to indicate to the
μ
PD98405
that the transaction's target device is ready to input/output
data. During the
μ
PD98405 DMA read operation, the
RDY_B signal should go low when valid data is present on
AD31 to AD0. During the
μ
PD98405 DMA write operation,
the ATTN_B signal should go low when the target device is
ready to accept data.
The timing at which the
μ
PD98405 samples the RDY_B and
ABRT_B signals can be changed to one clock earlier (early
mode) by setting an internal register (GMR).
ATTN_B
294
O
TTL
GNT_B
291
I
TTL
RDY_B
23
I
TTL