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CHAPTER 5 SAR FUNCTION
125
3. MTA is the only register related to mailboxes that can be updated and controlled by the
host. MSH, MSL, MWA, and MBA must be written by the host during initialization but
cannot be modified while the
μ
PD98405 is performing transmission or reception. The
μ
PD98405 frequently accesses and controls these registers during transmission/reception.
Modifying them during transmission/reception will thus cause a malfunction.
Figure 5-5. Mailbox Structure
MSH,MSL
MBA
MWA
MTA
5.3.2 Mailbox Operation
The
μ
PD98405 increments the write pointer (MWA) every time it writes an indication. Each time an
indication is written, the
μ
PD98405 sets the MM bit of the GSR register corresponding to the mailbox, and
generates an interrupt, provided it is not masked.
If the bottom address (MBA) is reached while the
μ
PD98405 is updating the write pointer (MWA), the MWA
jumps to the start address (MSL).
The read pointer (MTA) is used to prevent the
μ
PD98405 from overwriting an indication that has not yet
been read by the host. The read pointer (MTA) for each mailbox is managed and updated by the host. Each
time the host reads an indication from a mailbox, it writes, to the read pointer (MTA), the address next to that of
the indication which has just been read. MTA can be updated only by the host, and read only by the
μ
PD98405.
If the write pointer (MWA) is set to the same address as the read pointer (MTA), the
μ
PD98405 sets, in the
GSR register, the MF bit corresponding to the mailbox to indicate mailbox full (MF) status, and generates an
interrupt provided it is not masked. In MF status (MWA = MTA), the
μ
PD98405 does not issue subsequent
indications to the mailbox. The host must read an indication from the mailbox in MF status, and immediately
update MTA.