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CHAPTER 2 PIN FUNCTIONS
27
2.3 PIN FUNCTIONS
The
μ
PD98405 is packaged in a 304-pin package. See
Chapter 4
for details of the pin functions and notes
on use.
2.3.1 PHY Layer Device Interface Signals
Signals for interfacing with the PHY layer device are classified into UTOPIA interface signals used to transfer
ATM cells between the
μ
PD98405 and PHY device and PHY control interface signals used to control the PHY
device.
The
μ
PD98405 supports octet-level and cell-level modes for the UTOPIA interface. These modes are
selected by setting the UOC bit of the GMR register.
The PHY layer device interface signals are for use with an external PHY layer device. When using the
internal PHY layer, leave other than the common pins open. Even when using the internal PHY layer, however,
an external receive FIFO can be connected to the
μ
PD98405 via a UTOPIA interface. (See
Section 4.3.1 (3)
.)
(1) UTOPIA interface
(1/2)
Symbol
Pin No.
I/O
I
I/O level
Function
Rx7-Rx0
(Rx1, Rx0:
Common with
TFKC and
TFKT pins)
235 - 242
TTL
Receive Data Bus
Rx7-Rx0 is an 8-bit input bus used to receive the network
traffic in byte form from the PHY layer device. The eight bits
are input to the
μ
PD98405 in synchronization with the rising
edge of RCLK.
Rx7-Rx2: Internal pull-down signal. Leave open when not
used.
Rx1
: Connect a pull-down resistor when not used.
Rx0
: Connect a pull-up resistor when not used.
Receive Start of Cell
The RSOC signal is input in synchronization with the first
byte of cell data received from the PHY layer device. Keep
this signal high while the first byte of the header is being
input to Rx7-Rx0.
These pins are connected to internal pull-down resistors.
Receive Enable
The RENBL_B signal indicates to the PHY layer device that
the
μ
PD98405 is ready to accept data in the next clock
cycle.
RSOC
247
I
TTL
RENBL_B
246
O
TTL