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參數(shù)資料
| 型號(hào)： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 74/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
70
Lucent Technologies Inc.
Application Briefs
(continued)
Available Tools for Evaluation of the T7256
(continued)
spulse
'pol/mag'
Enable single pulse mode.
Single pulse mode is for performing pulse template
tests on the U- and S/T-interfaces. For the U-interface,
the chip is placed into a mode in which it periodically
(every 125
μ
s) outputs a single isolated pulse whose
magnitude and polarity depend on the ‘pol/mag’ com-
mand line parameter, which can be +1, +3, –1, and –3.
For the S/T-interface, the I.430-defined Loop C is set up
so that S/T test equipment such as the Siemens*
K1403 can transmit a fixed pattern and expect to
receive the same pattern (this is a common way of per-
forming pulse template tests on the S/T-interface).
Prior to activating this mode, the U- and S/T-interfaces
should be disconnected from the SCNT1-based prod-
uct until after the mode is entered, at which point they
may be reconnected.
eye
Enable EYE pattern mode.
This mode is for viewing the eye pattern of the received
signal at the input to the slicer. This gives a good indi-
cation of the receiver performance and shows the
effect of impairments such as NEXT. The eye pattern
signal is available at BNC connector J5.
srst
Performs a h/w reset of SCNT1.
help
Displays a list of available commands.
Using the SPEC_V2
To use the SPEC_V2, connect it to a terminal emulator
configured for 9600 baud, 8-bit, 1 stop bit, no parity, full
duplex, and XON/XOFF flow control. A +5 V supply
should be connected to connector J3 using the screw-
terminal block provided with the board (the +5 V lead
gets connected to pin 1 of J3, and the return lead gets
connected to pin 2). When power is applied, LED D1
should illuminate to indicate that there is power to the
board. Once connected to the UUT, the SPEC_V2
should not be powered down, since it may cause the
UUT to malfunction.
SPEC_V2-to-UUT Interface Description
The unit under test (UUT) is connected to J1 on the
SPEC_V2 board via one of the two supplied ribbon
cable assemblies. If the SCNT1-RDB board is being
used as the UUT, the ribbon cable assembly with the
16-pin ribbon header at both ends can be used and will
be connected to the SCNT1-RDB at connector J3 (the
general-purpose interface). If such a connector is not
available on the UUT, the ribbon cable assembly with a
16-pin dual header on one end and a PLCC-44 IC clip
on the other can be used to clip directly to the SCNT1
chip on the UUT. If the SCNT1 is socketed or otherwise
not accessible with an IC clip, some other method of
access to the required signals must be provided.
The J1 connector pinouts are shown in Table 34. The
J1 signals are assigned such that a straight 16-pin rib-
bon cable assembly can be connected directly between
J1 of the SPEC_V2 and the general-purpose interface,
J3, of the T7237/56 Reference Design Board (SCNT1-
RDB). In this case, the signal CKOUT should be routed
through a BNC cable for isolation and shielding. Sig-
nals that are provided on J3 of the SCNT1-RDB but not
used by the SPEC_V2 are noted in the last column. If
an alternative cabling arrangement is used, note that
the signals in the Signal Name column must be pro-
vided at the UUT interface point unless otherwise
noted (GND
D
need be provided only once).
* Siemens is a registered trademark of Siemens Aktiengesellschaft.
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