參數(shù)資料
型號： T7234
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 37/116頁
文件大?。?/td> 1056K
代理商： T7234
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
33
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 17. Q-Channel Bits (Address 0Dh)
These register bits are forced to 1 if MULTIF = 1 (register GR0, bit 5) and during RESET.
Table 18. S Subchannels 1—5 (Address 0Eh—12h)
These register bits have no effect on device operation and are set to 0 if MULTIF = 1. Refer to the S/T-Interface
Multiframing Controller Description section for more detail on using S and Q channels.
Reg
MCR0
R/W
R
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
Q1
Bit 2
Q2
Bit 1
Q3
Bit 0
Q4
Register
MCR0
Bit
0—3
Symbol
Q[4:1]
Name/Description
Q-Channel Bits.
Four bits reflecting the four Q bits (Q1—Q4) received
in the last completed multiframe. Bits are loaded at the end of the mul-
tiframe.
Reg
MCR1
MCR2
MCR3
MCR4
MCR5
Default State on RESET
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
—
—
—
—
—
—
Bit 6
—
—
—
—
—
—
Bit 5
—
—
—
—
—
—
Bit 4
—
—
—
—
—
—
Bit 3
SC11
SC21
SC31
SC41
SC51
0
Bit 2
SC12
SC22
SC32
SC42
SC52
0
Bit 1
SC13
SC23
SC33
SC43
SC53
0
Bit 0
SC14
SC24
SC34
SC44
SC54
0
Register
MCR1
MCR2
MCR3
MCR4
MCR5
Bit
0—3
0—3
0—3
0—3
0—3
Symbol
SC1[4:1]
SC2[4:1]
SC3[4:1]
SC4[4:1]
SC5[4:1]
Name/Description
S Subchannel 1.
S Subchannel 2.
S Subchannel 3.
S Subchannel 4.
S Subchannel 5.
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T7234A 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement
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