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參數(shù)資料
| 型號： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 22/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
18
Lucent Technologies Inc.
S/T-Interface Description
At the S/T-interface, the 4-wire line transceiver meets
the ANSI T1.605 standard, ITU-T I.430 recommenda-
tion, and ETSI ETS 300 012 when used with the proper
line interface circuitry. Refer to the March 1996, T7903
ISA Multiport Wide Area Connection (ISA-MWAC)
Device Data Sheet (DS96-084ISDN). Appendix F of
the ISA-MWAC data sheet is an application brief that
contains detailed information concerning guidelines for
S/T line interface circuit design.
The S/T transceiver interprets the frames received from
the line and generates frames to be transmitted onto
the S/T link. It exchanges full-duplex 2B+D information
with the data flow matrix. The transceiver consists of
two sections, the transmitter and the receiver. The
transmitter is a voltage-limited current source. The
transmitted bits are timed by an internal 192 kHz clock
derived from the U-interface.
The transmitter employs a line coding technique
referred to in the standards as “pseudo-ternary coding
with 100% pulse width,” which is often referred to as
alternate space inversion (ASI) coding. ASI coding rep-
resents a logical 1 by the absence of a pulse and a log-
ical 0 by alternating positive and negative pulses. ASI
is a differential strategy, with positive and negative rails
connecting to the transformer. Current flows through
the transformer only when there is a voltage difference
on the two rails. When a logical one or mark is being
sent, meaning no current is desired, both rails go to a
high-impedance condition. When a positive logical zero
(space) is transmitted, the positive rail forces current to
the negative rail through the transformer. The reverse
occurs for a negative zero. Table 3 and Figure 10 illus-
trate the ASI coding method.
Table 3. Line Transmission Code
* Z = high impedance.
The line receiver is more complex. Since the loop
length to the subscriber(s) is variable, as is the number
of TEs on the loop (1 to 8), the receiver must be suffi-
ciently intelligent to adjust for widely varying input
waveforms. The receiver uses a self-adjusting voltage
threshold comparator to adapt to various loop lengths.
It also features a digital timing recovery circuit employ-
ing either adaptive or fixed timing modes.
The adaptive timing mode can be used on any loop
configuration (point-to-point, extended passive bus,
short passive bus) in which round trip delays are
between 0
μ
s and 42
μ
s and differential delays
between TEs are between 0
μ
s and 3.1
μ
s. This
exceeds the requirement in the standards, which is
0—2
μ
s (see, for example, ITU-T I.430 section A.2.1.3
(p. 58). A differential delay of 0
μ
s is meaningful in the
case of a line transmitter and line receiver directly con-
nected externally in a loopback configuration, so the
receiver can extract the 2B+D information correctly
from the transmitted stream.
A short passive bus configuration permits TEs to be
connected anywhere along the full length of the cable,
with the restriction that the total round trip delay must be
between 10
μ
s and 14
μ
s for all TEs. Thus, worst-case
differential delay between TEs can be as much as 4
μ
s.
If the differential delay is more than 3.1
μ
s, adaptive tim-
ing mode cannot be used. A fixed timing mode is avail-
able for this case. When using fixed timing, the input
stream is sampled 4.2
μ
s after the leading edge of each
192 kHz transmit bit interval. The fixed/adaptive timing
mode is controlled via the FTE pin if the TDM highway
is not enabled (TDMEN = 0 in register GR2, bit 5). Oth-
erwise, it is controlled via the FT microprocessor bit
(register GR2, bit 0).
5-2295 (C)
Figure 10. S/T-Interface ASI Example
Microprocessor Interface Description
The microprocessor interface, used to control and
monitor the device, is compatible with most general-
purpose serial microprocessor interfaces using a syn-
chronous mode of transmission. A detailed description
of the operation follows, and detailed timing information
is given in the Timing Characteristics section.
Registers
The on-chip registers are divided by major circuit block
and by status and control function. Microprocessor reg-
ister control bits associated with the control flow state
machine, eoc state machine, and multiframing control-
ler are ignored when those blocks are enabled (the
device controls the blocks automatically). When the
blocks are disabled, the control bits are used to drive
device operations. The functional summary of the reg-
isters and bits is shown in Figure 11.
Positive Rail
Z*
1
0
Negative Rail
Z*
0
1
Current
0
+1
–1
Logic
1
+0
–0
1
0
1
0
0
1
1
0
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