- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383875 > T7234 Compliance with the New ETSI PSD Requirement PDF資料下載
參數(shù)資料
| 型號： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 57/116頁 |
| 文件大小： | 1056K |
| 代理商： | T7234 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當(dāng)前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
53
Application Briefs
(continued)
T7256 Reference Circuit
(continued)
Power Status Leads
ANSI T1.601 Section 8.2.4 defines U-interface NT
power status bits ps1 and ps2. These bits are transmit-
ted across the U-Interface via the U maintenance chan-
nel. On the T7256, these bits are controlled by pins 8
and 9 (PS2E and PS1E). When the TDM highway is
used (NT1+ or TA modes), the ps1/ps2 bits are con-
trolled by internal registers that are written by an exter-
nal microprocessor. An NT1 typically has circuitry that
monitors the status of the power supply and sets ps1
and ps2 accordingly. In general, power status monitor-
ing circuitry is dependent on various system parame-
ters and requirements, and must be designed based on
the specific application’s requirements. For this reason,
there is no power status monitoring circuitry shown in
this design. Instead, pull-ups R1 and R2 in Figure 20
are provided to force a default indication of primary and
secondary power good status.
Fixed/Adaptive Timing Control
As detailed in Table 1, pin 7 of the T7256 controls
whether the S/T-interface will use fixed or adaptive tim-
ing recovery. When there is no connection to pin 7, an
internal 100K pull-up holds the pin high, which causes
the chip to default to adaptive timing recovery. JMP1 is
provided (see Figure 20) to change the timing recovery
mode to fixed timing by pulling pin 7 down through a
5.1 k
resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7234A | Compliance with the New ETSI PSD Requirement |
| T7237A | Compliance with the New ETSI PSD Requirement |
| T7256A | Compliance with the New ETSI PSD Requirement |
| T7288 | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| T7290A | DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7234A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7240 | 制造商:TE Connectivity 功能描述: |
| T7-241A5 | 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。