參數(shù)資料
型號(hào)： T7234
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 27/116頁
文件大?。?/td> 1056K
代理商： T7234
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
23
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 6. Global Device Control—S/T-Interface (Address 02h)
Reg
GR2
Default State
on RESET
R/W
R/W
Bit 7
STOA
1
Bit 6
ACTSEL
ACTMODE/
INT pin
Bit 5
TDMEN
1
Bit 4
U2BDLN
1
Bit 3
SXE
1
Bit 2
SRESET
1
Bit 1
Bit 0
FT
1
SPWRUD
1
Register
GR2
Bit
0
Symbol
FT
Name/Description
Fixed/Adaptive Timing Control.
Controls mode of timing recovery on S/T-inter-
face if TDMEN = 0 (register GR2, bit 5). If TDMEN = 1, FT is ignored.
0—Fixed timing.
1—Adaptive timing (default).
S/T-Interface Powerdown Control.
When 0, this bit forces the S/T-interface to
remain in a powerdown mode. This is the same low-power mode the S/T-interface
is in when the T7256 is in its IDLE state with no activity on the U- or S/T-interfac-
es. In this mode, all S/T-interface circuits are powered down, except for circuits
required to detect an activation request from a TE.
0—Powerdown.
1—Normal (default).
S/T-Interface Reset.
While 0, this bit causes a reset of the S/T-interface, initial-
izing the interface in the same manner as the external RESET pin. Must be set to
1 for normal operation.
0—Reset.
1—Normal (default).
S/T-Interface D-Channel Echo Bit Control.
Controls data in E channel from NT
to TE on S/T-interface. This bit must be cleared during 2B+D loopbacks to meet
ITU-T I.430 requirements.
0—All 0s.
1—Echoes D channel from S/T receive path (default).
Nontransparent 2B+D Loopback Control.
When 0, this bit causes a nontrans-
parent loopback of 2B+D data from U receiver to U transmitter upstream of the
data flow matrix. Note that this loopback path is not as close to the S/T-interface
as the transparent loopback initiated by U2BDLT (register ECR0, bit 6). This loop-
back may be useful for test purposes. When this bit is set, the upstream data (NT
to LT direction) will be forced to all 1s until either ACTR = 1 (register CFR1, bit 0)
or XPCY = 0 (register GR1, bit 5).
0—2B+D loopback. All 1s 2B+D data is automatically generated towards the
TE.
1—No loopback (default).
TDM Bus Select.
Selects functions of pins 4, 7, 8, and 9.
0—TDM bus functions. Pins 4, 7, 8, and 9 configured as FS, TDMDI, TDMDO,
and TDMCLK, respectively. See DFR1 and TDR0 registers for TDM bus
programming details. Microprocessor register bits GR11, GR12, and GR20
control the PS2, PS1, and FT functions.
1—No TDM bus. Pins 4, 7, 8, and 9 configured as SYN8K/LBIND, FTE, PS2E,
and PS1E, respectively (default).
GR2
1
SPWRUD
GR2
2
SRESET
GR2
3
SXE
GR2
4
U2BDLN
GR2
5
TDMEN
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