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參數(shù)資料
| 型號： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 108/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
104
Lucent Technologies Inc.
Questions and Answers
(continued)
Miscellaneous
(continued)
Q59:
What is the state of the T7256 TDM bus output
when the unused bits of the D-channel octet are
transmitted
A59:
The T7256 3-states the TDM bus output when B-
and D-channel information is not transmitted to
the TDM bus. This includes the 6-bit interval in
the D-channel octet.
Q60:
What is the purpose of the ACTSEL bit in register
GR2 bit 6
A60:
This bit is to provide compatibility with the ANSI
T1.601 and ETSI ETR 080 standards. The 1992
version of T1.601 (the most recent as of this writ-
ing) specifies that, upon a loopback 2 eoc
request, the NT1’s 2B+D data should be looped
back immediately and the upstream (NT-to-LT)
act bit should be set to 0. ANSI specified that the
upstream act bit should be set to 0 to indicate to
the LT that end-to-end data transparency (TE-to-
LT) is interrupted during a loopback 2. The fact
that 2B+D data is looped back immediately
means that upstream data transparency at the
NT is established independent of the status of the
act bit from the LT. Normally, upstream data
transparency at the NT is dependent on act = 1
being received from the LT. The reason that loop-
back 2 transparency criteria differ is that there is
no guarantee that the NT1 will receive
act = 1 from the LT. Consider the case where an
LT wants to activate the U-interface and perform
a loopback 2 test on an NT1 with no TE con-
nected. In this case, the LT will never receive
act = 1 since, prior to the loopback 2 request,
act = 0 because there is no TE attached, and
after the loopback 2 request, act = 0 because
layer 1 transparency is interrupted. Since the LT
will never receive act = 1 from the NT1, it will
never send act = 1 back to the NT1. Since the
NT1 receipt of act = 1 normally enables upstream
transparency, ANSI chose to make an exception
to the data transparency requirements in this
case and enable upstream transparency immedi-
ately upon receipt of the loopback 2 eoc com-
mand at the NT1.
The major difference between the ANSI and ETSI
standards with regard to how the NT1 handles a
loopback 2 request lies in what happens to the
upstream act bit. ANSI’s position is that act
should be set to 0 because a loopback 2 is an
interruption to layer 1 transparency. ETSI’s posi-
tion is that the state of the act bit should only be
dependent on whether or not the NT1 is receiving
INFO 3 from the TE (this is consistent with ANSI
T1.601 paragraph 6.4.6.4 and ETSI ETR 080
paragraph A.10.1.5.1). During a loopback 2, the
T7256 will always receive INFO 3 at the S/T-inter-
face (even if there is no TE attached) because it
loops back its S/T transmit signal and synchro-
nizes itself to that signal. Therefore, the possibility
that LT will never receive act = 1 from the NT
does not exist under these rules. As a result, no
special exceptions need to be applied to the case
of loopback 2 in ETSI. For example, again con-
sider the case where an LT wants to activate the
U-interface and perform a loopback 2 test on an
NT1 with no TE connected. The NT1 will synchro-
nize to its own S/T signal and detect INFO 3. This
will cause act = 1 to be transmitted upstream. The
LT will detect act = 1 and set its downstream act =
1. When the NT detects the downstream act = 1,
it will enable upstream data transparency. The
handling of the act bit and transparency in this
case is the same as for a normal activation.
In the ETSI standard, transparency at the NT dur-
ing loopback 2 is dependent upon the reception
of the act bit from the LT, i.e., if act = 1, loopback
transparency is established, and if act = 0, loop-
back data is forced to all 1s. The LT won’t send
act = 1 until it receives act = 1 from the NT. The
NT will not send act = 1 to the LT until it receives
an INFO 3 indication (i.e., until its S/T-interface is
synchronized as described in the register GR2
ACTSEL bit definition). Thus, data transparency
requires that the NT1 set its upstream act bit to 1.
There is a contribution that has been voted onto
the ANSI T1E1.4 living list that changes the act
bit behavior during loopback 2 to match that
specified for ETSI (contribution #T1E1.4/92-089).
Thus, the next issue of the T1.601 standard will
bring the ANSI and ETSI standards into harmony
as pertains to handling of the act bit during a
loopback 2.
相關(guān)PDF資料 |
PDF描述 |
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| T7234A | Compliance with the New ETSI PSD Requirement |
| T7237A | Compliance with the New ETSI PSD Requirement |
| T7256A | Compliance with the New ETSI PSD Requirement |
| T7288 | CEPT/E1 Line Interface(CEPT/E1 線接口) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7234A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7240 | 制造商:TE Connectivity 功能描述: |
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