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參數(shù)資料
| 型號： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 7/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
3
Table of Contents
(continued)
Figures
Page
Figure 1. Block Diagram......................................................................................................................................... 5
Figure 2. Pin Diagram............................................................................................................................................. 5
Figure 3. Applications of T7256............................................................................................................................ 10
Figure 4. U-Interface Frame and Superframe ...................................................................................................... 12
Figure 5. U-Interface Superframe Bit Groups....................................................................................................... 13
Figure 6. Frame Structures of NT and TE Frames............................................................................................... 14
Figure 7. Details of NT and TE Frames................................................................................................................ 15
Figure 8. Multiframing—S Subchannels and Q Subchannels .............................................................................. 16
Figure 9. U-Interface Quat Example..................................................................................................................... 17
Figure 10. S/T-Interface ASI Example.................................................................................................................. 18
Figure 11. Functional Register Map (Addresses and Bit Assignments)............................................................... 19
Figure 12.
NEC
and
Motorola
Microprocessor Port Connections......................................................................... 39
Figure 13.
Intel
Microprocessor Port Connections ............................................................................................... 39
Figure 14. Synchronous Microprocessor Port Interface Format........................................................................... 40
Figure 15. TDM Bus Time-Slot Format................................................................................................................. 42
Figure 16. B1-, B2-, D-Channel Routing............................................................................................................... 43
Figure 17. Location of the Loopback Configurations (Reference ITU-T I.430 Appendix I)................................... 44
Figure 18. STLED Control Flow Diagram............................................................................................................. 47
Figure 19. External Stimulus/Response Configuration......................................................................................... 51
Figure 20. T7256 Stand-Alone Reference Circuit-A............................................................................................. 54
Figure 21. T7256 Stand-Alone Reference Circuit-B............................................................................................. 55
Figure 22. T7256 NT1/TA Application Block Diagram.......................................................................................... 59
Figure 23. MC68302 to T7256 Interface Diagram................................................................................................ 62
Figure 24. SCNT1-RDB EPLD Schematic............................................................................................................ 64
Figure 25. SCNT1-RDB EPLD ADHL Design Files.............................................................................................. 65
Figure 26. SCNT1-RDB EPLD Timing (8-bit)....................................................................................................... 66
Figure 27. SCNT1-RDB EPLD Timing (7-bit)....................................................................................................... 67
Figure 28. TDM Bus Timing.................................................................................................................................. 76
Figure 29. Timing Diagram Referenced to SYN8K............................................................................................... 77
Figure 30. RESET Timing Diagram...................................................................................................................... 77
Figure 31. Switching Test Waveform.................................................................................................................... 78
Figure 32. Transceiver Impedance Limits ............................................................................................................ 82
Figure 33. Receiver Bias...................................................................................................................................... 90
Figure 34. T7256 S/T Line Interface Scheme....................................................................................................... 94
Figure 35. T7903 S/T Line Interface Scheme....................................................................................................... 94
Figure 36. T7250C S/T Line Interface Scheme.................................................................................................... 95
Figure 37. T7903 to T7256 Direct-Connect Scheme............................................................................................ 96
Figure 38. T7250C to T7256 Direct-Connect Scheme......................................................................................... 96
Figure 39. T7903 to T7256 Direct-Connect Scheme with External S/T-Interface ................................................ 97
Figure 40. T7250C to T7256 Direct-Connect Scheme with External S/T-Interface.............................................. 98
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