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參數(shù)資料
| 型號(hào)： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 64/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
60
Lucent Technologies Inc.
Application Briefs
(continued)
T7256 Configuration
(continued)
4. The upstream B-channel source will be either the
S/T-interface (if a TE has a call active) or the TDM
highway (if an analog phone has a call active). Each
B channel can be sourced from the TDM highway or
the S/T-interface independent of the other B chan-
nel. The source of the upstream B channels is con-
trolled by register DFR0, bits 1 and 0 (for B1) and
bits 3 and 2 (for B2). These bits must be controlled
dynamically depending on whether an analog
phone or a TE is requesting the B channel. A sug-
gested approach to B-channel control is to default
to the S/T-interface (i.e., the TEs) and switch to the
TDM highway when it is determined that a call is
being placed/received on the analog phone (i.e.,
after call setup has been established via the D
channel as described in item #2, above). For exam-
ple, if a B1 call is placed on an analog phone,
DFR0, bit 1 must be changed from a 1 to a 0 to
allow the POTS circuitry to source the upstream B1
channel data. All the other bits in DFR0 remain set
to 1.
Register DFR1, bits 5 and 6 control B1 and B2
channel data (respectively) from the U-interface to
the TDM highway. It may be necessary to keep the
B1 and B2 time slots disabled (3-stated) when the
analog phones are not in use to keep the codecs
quiet. A 5.1 k
pull-up resistor on the TDMDO pin
should be used to ensure that the TDM data is all
1s. Some codecs can be quieted by disabling the
codec frame strobe signal.
5. When the TDM highway is enabled by setting
TDMEN = 0, TDMCLK and FS will not become
active until at least one of the bits 2—7 in register
DFR1 are enabled (set to 0).
D-Channel Priority
One issue in this application concerns the D-channel
priority mechanism because the D channel must be
shared between the TA circuitry and any TEs that are
connected to the S/T-interface. Below is an approach
for implementing the D-channel priority mechanism.
1. Normally, the D channels from the TE should be
routed directly through to the switch. Thus, the NT1/
TA simply looks like an NT1, passing data directly
between the S/T- and U-interfaces.
2. If a POTS phone needs to access the D channel
(due to an incoming or outgoing call request as
described in item #2 of the previous section), it
should set SXE = 0 (register GR2, bit 3). This will
cause any TEs currently accessing the D channel to
relinquish the D channel due to a collision detection
(i.e., the TE’s outgoing D bit will differ from its
incoming E bit).
3. The POTS controller should delay 1.5 ms, then set
UXD = 0 (register DFR1, bit 0) to allow local control
of the upstream D channel. Then it can assume
control of the D channel and begin to transmit and
receive call control packets via the HDLC formatter.
The 1.5 ms delay guarantees that at least seven 1s
will be transmitted in the upstream D-channel data
stream before the local controller sends the opening
flag of its first packet. Thus, if the last bit that a TE
transmitted on the D channel (before SXE = 0 was
set) was a 0, the transmission of at least seven 1s
will cause an abort HDLC message to be recog-
nized by the switch, which properly notifies the
switch that the TE that was in the process of send-
ing a packet aborted that transmission.
4. When the POTS controller has completed its D-
channel message, it should set SXE = 1 to relin-
quish control of the D channel.
More intelligence can be built into the D-channel algo-
rithm if desired. For example, since the downstream D-
channel messages are always being monitored, it is
possible to determine whether a call setup to a TE is in
progress. If so, the POTS controller can hold off a local
TA call request until the TE call setup is complete. In
addition, after each D-channel access, the POTS con-
troller can allow adequate time for a TE to exchange
call control messages with a switch before taking over
the D channel again. The timing for these sequences
would be managed by the TA controller software.
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