參數(shù)資料
型號： T7234
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 44/116頁
文件大小： 1056K
代理商： T7234
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
40
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Timing
(continued)
Note: If SCLK is initially low, it must be held high for >300
μ
s before its first falling edge. From that point forward, the above timing applies.
5-2302 (C)
Figure 14. Synchronous Microprocessor Port Interface Format
SCLK
SDI
SDO
1
2
3
4
5
6
7
8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
COMMAND
MSB
LSB
MSB
LSB
SHIFT IN
SAMPLE SHIFT IN
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI0
DI1
DO7
DO6
DO5
DO4
DO3
DO2
DO0
DO1
DON'T CARE
≤
300 μs
1
CA7
≥
10 μs
≥
10 μs
ADDRESS
DATA SHIFT OUT
Figure 14 shows the basic transfer format. All data
transfers are initiated by the microprocessor, although
the interrupt may indicate to the microprocessor that a
register read or write is required. The microprocessor
should normally hold the SCK pin high during inactive
periods and only make transitions during register trans-
fers. The maximum clock rate of SCK is 960 kHz. Data
changes on the falling edge of SCK and is latched on
the rising edge of SCK.
Each complete serial transfer consists of 2 bytes
(8 bits/byte). The first byte of data received over the
SDI pin from the microprocessor consists of
command/address information that includes a 5-bit reg-
ister address in the least significant bit positions
(CA4—CA0) and a 3-bit command field in the most sig-
nificant bit positions (CA7—CA5). The byte is defined
as follows:
I
Bits CA7—CA5: 001 = read, 010 = write, all other bit
patterns will be ignored.
I
Bits CA4—CA0: 00000 = register address 0,
00001 = register address 1, etc.
The second byte of data received over the SDI pin con-
sists of write data for CA7—CA5 = 010 (write) or don't
care information for CA7—CA5 = 001 (read).
The data transmitted over the SDO pin to the micropro-
cessor during the first byte transfer is a don't care for
both read and write operations. The second byte trans-
mitted over the SDO pin consists of read data for CA7—
CA5 = 001 (read) or don't care information for CA7—
CA5 = 010 (write).
In order for the T7256 to recognize the identity (com-
mand/address or data) of the byte being received, it is
required that the time allowed to transfer an entire
instruction (time from the receipt of the first bit of the
command/address byte to the last bit of the data byte)
be limited to less than 300
μ
s. This limits the minimum
SCK rate to 60 kHz. If the complete instruction is
received in less than 300
μ
s, the T7256 accepts the
instruction immediately and is ready to receive the next
instruction after a 10
μ
s delay. If the complete instruc-
tion is not received within 300
μ
s, the bits received in
the previous 300
μ
s are discarded and the interface is
prepared to receive a new instruction after a 10
μ
s
delay. In addition, a minimum 10
μ
s delay must exist
between the command/address and data bytes.
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