參數(shù)資料
型號： T7234
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 49/116頁
文件大?。?/td> 1056K
代理商： T7234
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
45
Modes of Operation
To provide flexibility in the system architecture, the T7256 transceiver can operate in stand-alone mode (no micro-
processor) to provide basic NT1 functionality or it can operate under microprocessor control through the serial
interface to provide enhanced NT1 operation. In stand-alone mode, the T7256 automatically handles U- and
S/T-interface activation, control, and maintenance according to the ANSI T1.601 and ITU-T I.430/ANSI T1.605
standards. The device is configured for this mode via internal pull-ups and pull-downs and microprocessor register
default values during an external RESET. Table 26 shows the transceiver control pins that may be relevant in stand-
alone mode.
Table 26. Stand-Alone Mode
In microprocessor mode, the T7256 supports all the features of stand-alone mode, plus allows enhanced control
including S/Q-channel support, TDM highway access, and manual eoc and U overhead bit manipulation. The
microprocessor port can be accessed at any time via the SDI, SDO, and SCK pins (see Microprocessor Interface
Description and Timing Characteristics sections for details). Table 27 shows the transceiver control pins that may
be relevant in microprocessor mode, or whose operation may change based on register settings.
Table 27. Microprocessor Mode
Pin
2
Symbol
OPTOIN
Function
Maintenance pulse streams are decoded and automatically implemented us-
ing the ANSI state machine requirements.
Performs the SYN8K or LBIND depending on the state of SYN8K_CTL/SDI
(pin 12) during an external RESET.
Performs the FTE function. Selects the S/T-interface timing recovery mode.
Performs the PS2E function. Controls the PS2 bit in the transmit U-interface
data stream.
Performs the PS1E function. Controls the PS1 bit in the transmit U-interface
data stream.
Performs the ACTMODE function. Controls the act bit in the transmit
U-interface data stream during 2B+D loopbacks.
Held high or low on powerup or RESET to control SYN8K/LBIND/FS (pin 4).
Held high or low on powerup or RESET to control automatic activation
attempt.
Resets the device. The states of SCK, SDI, and INT are read upon exiting
reset state.
4
SYN8K/LBIND/FS
7
8
FTE/TDMI
PS2E/TDMDO
9
PS1E/TDMCLK
11
ACTMODE/INT
12
15
SYN8K_CTL/SDI
AUTOACT/SCK
43
RESET
Pin
2
4
6
7
8
9
11
12
14
15
Symbol
OPTOIN
Comment
Controlled by microprocessor bit AUTOCTL (register GR0).
Controlled by microprocessor bit TDMEN (register GR2).
Controlled by microprocessor bit AUTOCTL (register GR0).
Controlled by microprocessor bit TDMEN (register GR2).
Controlled by microprocessor bit TDMEN (register GR2).
Controlled by microprocessor bit TDMEN (register GR2).
Interrupt output for the microprocessor interface.
Serial data input for the microprocessor interface.
Serial data output for the microprocessor interface.
Master clock input for the microprocessor interface.
SYN8K/LBIND/FS
ILOSS
FTE/TDMDI
PS2E/TDMDO
PS1E/TDMCLK
ACTMODE/INT
SYN8K_CTL/SDI
SDO
AUTOACT/SCK
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