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參數(shù)資料
| 型號(hào)： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 41/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
37
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 23. Maintenance Interrupt Register (Address 17h)
These bits are cleared during RESET.
Table 24. Maintenance Interrupt Mask Register (Address 18h)
Reg
MIR0
R/W
R
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
—
Bit 2
EMINT
Bit 1
ILINT
Bit 0
QMINT
Register
MIR0
Bit
0
Symbol
QMINT
Name/Description
Quiet Mode Interrupt.
Activates (set to 1) when the ANSI maintenance
state machine detects a request on the OPTOIN pin for the device to en-
ter the quiet mode. Bit is cleared on read.
0—No quiet mode request.
1—Quiet mode requested.
Insertion Loss Interrupt.
Activates (set to 1) when the ANSI mainte-
nance state machine has detected a request on the OPTOIN pin for the
device to transmit the SN1 tone on the U-interface. Bit is cleared on read.
0—No SN1 tone request.
1—SN1 tone requested.
Exit Maintenance Mode Interrupt.
Activates (set to 1) when the ANSI
maintenance state machine detects a request on the OPTOIN pin for the
device to exit the current maintenance mode. Bit is cleared on read.
0—No exit request.
1—Exit requested.
MIR0
1
ILINT
MIR0
2
EMINT
Reg
MIR1
Default State on RESET
R/W
R/W
Bit 7
—
—
Bit 6
—
—
Bit 5
—
—
Bit 4
—
—
Bit 3
—
—
Bit 2
EMINTM
1
Bit 1
ILINTM
1
Bit 0
QMINTM
1
Register
MIR1
Bit
0
Symbol
QMINTM
Name/Description
Quiet Mode Interrupt Mask.
0—QMINT interrupt enabled.
1—QMINT interrupt disabled (default).
Insertion Loss Interrupt Mask.
0—ILINT interrupt enabled.
1—ILINT interrupt disabled (default).
Exit Maintenance Mode Interrupt Mask.
0—EMINT interrupt enabled.
1—EMINT interrupt disabled (default).
MIR1
1
ILINTM
MIR1
2
EMINTM
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