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| 型號： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 72/116頁 |
| 文件大小： | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
68
Lucent Technologies Inc.
Application Briefs
(continued)
Interfacing the T7256 to the Motorola
68302
(continued)
To enable the TDMCLK and FS signals and generate
the FS signal in the proper time slot, the following
T7256 register bits must be programmed:
Register GR2, bit 5 (TDMEN) = 0.
Register DFR1, bits 7:5 (TDMDU, TDMB2U, TDMB1U)
= 000.
Register TDR0, bit 3:0 (FSP, FSC[2:0]) = 1111
(default).
Detailed information on T7256 activation control and
configuration of the microprocessor registers can be
found in the Application Briefs, Using the T7256 in a
Combination NT1/TA Environment section in this docu-
ment.
As an example of programming the MC68302 SIMODE
register bits for PCM mode, the following settings will
enable PCM mode and route the B2 channel to SCC1,
the B1 channel to SCC2, and the D channel to SCC3.
The ISDN signaling protocol stack (Q.931 and LAPD)
would communicate via SCC3, and any higher-layer
data protocol such as V.120 or V.110 would communi-
cate via SCC1 and SCC2, as required.
SETZ = 0, SYNC = 1, SDIAG1:SDIAG0 = 00, SDC2 =
0, SDC1 = 0, B2RB:B2RA = 01, B1RB:B1RA = 10,
DRB:DRA = 11, MSC3 = 0, MSC2 = 0, and MS1:MS0 =
01.
T7256 Serial Microprocessor Interface Support
The MC68302 SCP interface is a 3-wire serial interface
that may be directly connected to the T7256 micropro-
cessor interface. The SCP interface is implemented in
the MC68302 hardware, and the only software interac-
tion required is to set up the SCP interface, to transmit/
receive SCP bytes, and to respond to SCP events (the
SCP interrupt).
There are several points to note when interfacing the
T7256 to the MC68302 microprocessor interface.
1. Register bit CI (clock invert) in the MC68302
SPMODE register should be set to 1 to invert the
MC68302 SCP clock in order to meet the T7256
microprocessor timing specifications.
2. The MC68302 SCP clock, SPCLK, may be pro-
grammed to run as high as 4.096 MHz. The mini-
mum rate of the SCP SPCLK, assuming the slower
16.384 MHz version of the MC68302 with a maxi-
mum divide-down prescale of 64, is 256 kHz. The
minimum and maximum rates of the T7256 SCK are
60 kHz and 960 kHz, respectively, and care should
be taken to ensure that the MC68302 is pro-
grammed to a clock rate that is compatible with
T7256.
3. Every T7256 access consists of two 8-bit transfers,
where the first is the command/address byte and
the second is the data byte. There must be a delay
of 10
μ
s between every 8-bit register access to
meet the T7256 microprocessor timing specifica-
tions. The back-to-back byte transmit delay of the
MC68302 SCP at the slowest SPCLK rate of
256 kHz can be anywhere from two to eight clocks,
or 7.8
μ
s to 31.25
μ
s. To ensure that the 10
μ
s delay
requirement is met, the MC68302 software must not
send the second byte of the 2-byte sequence for at
least 10
μ
s after the SCP processor clears the
DONE bit in the SCP transmit/receive buffer
descriptor (refer to Section 4.6.2 of the Motorola
MC68302 User Manual for further information).
4. During 2-byte data transfer over the MC68302 SCP,
8 bits will be shifted into the SCP receive buffer for
every 8 bits shifted out. For a T7256 read, the first
byte in the receive buffer should be discarded and
the second byte will contain the read data from the
T7256. For a write, both bytes should be discarded
from the SCP receive buffer.
5. The T7256 microprocessor interface lacks an
enable pin to permit multiple device communication
on a single MC68302 SCP. In these applications,
the T7256 microprocessor interface can be enabled/
disabled using a microprocessor parallel port pin to
control a 3-state buffer at SCK (pin 15).
An alternative method of interfacing the MC68302 to
the T7256 microprocessor interface is to use three
MC68302 parallel port pins (e.g., PB0, PB1, and PB2
in Figure 23) programmed as outputs and supporting
the T7256 microprocessor interface in software. The
timing of the SCK, SDI, and SDO signals can be imple-
mented in software with a minimum amount of code.
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