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參數(shù)資料
| 型號： | T7234 |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 20/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7234 |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
16
Lucent Technologies Inc.
S/T-Interface Frame Structure
(continued)
The T7256 supports multiframing on the S/T-interface
in conjunction with an external microprocessor that is
used to enable multiframing and transmit and receive
S- and Q-channel messages. When multiframing is
enabled, the M bit in the NT-to-TE direction is set to a
one every 20 frames and the FA bit is set to one every
five frames. The TE recognizes these states and, in
returned frames immediately corresponding to those in
which the NT set the FA bit, replaces the FA bit it sends
to the NT with a Q bit (Q1 through Q4). Q1 is returned
for each frame in which both the M and FA bits were set
to one by the NT, with Q2 through Q4 following at five-
frame intervals. (See Figure 8.)
The S-bit position in the NT-to-TE direction is divided
into five 4-bit subchannels during multiframing: SC1—
SC5. Message sets for subchannels SC3—SC5 are
not currently defined, and a message set for SC2 is
defined only in ANSI T1.605, but not ITU I.430 (see the
S/T-Interface Multiframing Controller Description sec-
tion for more details). Figure 8 indicates the location of
the various S-subchannel bits during multiframing.
5-2481.b (C)
Figure 8. Multiframing—S Subchannels and Q Subchannels
9
1
9
5
4
20
1
2
3
7
8
10 11 12 13 14 15
FA = 1
18 19 20
1
2
19
6
16 17
FA = 1
5
4
20
2
3
7
8
10 11 12 13 14 15
18 19 20
1
2
19
6
16 17
FA = 1
FA = 1
FA = 1
FA = Q1
FA = Q2
FA = Q3
FA = Q4
FA = Q1
(NT TO TE)
M BIT = 1
IN FRAME #1
MARKS START
OF MULTIFRAME
(TE TO NT)
THE TE-TO-NT TRANSMISSION
HAS A NOMINAL 2-bit DELAY
RELATIVE TO THE NT-TO-TE FRAMES.
S BITS OCCUR IN BIT 37
OF EACH NT-TO-TE FRAME.
S-SUBCHANNEL #1 BITS—
SC11, SC12, SC13, AND SC14
APPEAR IN FRAMES 1, 6, 11,
AND 16.
S-SUBCHANNEL #2 BITS—
SC21, SC22, SC23, AND SC24
APPEAR IN FRAMES 2, 7, 12,
AND 17.
Q BITS OCCUR EVERY FIVE FRAMES. THERE ARE
FOUR Q BITS PER MULTIFRAME IN THE FA BIT
POSITION (BIT 14) OF FRAMES 1, 6, 11, AND 16.
20-FRAME MULTIFRAME
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| T7234A | Compliance with the New ETSI PSD Requirement |
| T7237A | Compliance with the New ETSI PSD Requirement |
| T7256A | Compliance with the New ETSI PSD Requirement |
| T7288 | CEPT/E1 Line Interface(CEPT/E1 線接口) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7234A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Compliance with the New ETSI PSD Requirement |
| T7237A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Compliance with the New ETSI PSD Requirement |
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