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3.6.3
Peripheral Selection After Device Reset
3.6.4
PINMUX0 Register Description
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 3-16. DM6446 Multiplexed Peripheral Pins and Multiplexing Controls (continued)
PRIMARY
(DEFAULT)
FUNCTION
GPIO:
GPIO[37, 39:41]
SECONDARY
REGISTER/PIN
(3)
CONTROL
PinMux1:
SPI
TERTIARY
REGISTER/PIN
(3)
CONTROL
MULTIPLEXED
PERIPHERALS
SECONDARY
(1)
FUNCTION
TERTIARY
(2)
FUNCTION
SPI, GPIO
SPI:
SPI_EN0,
SPI_CLK,
SPI_DI, SPI_DO
SPI:
SPI_EN1
I2C:
SCL, SDA
SPI, ATA, GPIO
I2C, GPIO
GPIO:
GPIO[42]
GPIO:
GPIO[43:44]
GPIO:
GPIO[45]
GPIO:
GPIO[46]
ATA:
HDDIR
PinMux1:
SPI
PinMux1:
I2C
PinMux0:
HDIREN
PWM0, GPIO
PWM1, VPBE
(RGB666/RGB888),
GPIO
PWM2, VPBE
(RGB666/RGB888),
GPIO
ClockOut0, GPIO
ClockOut1, TIMER0,
GPIO:
GPIO[49]
GPIO
ATA, GPIO
PWM0
VPBE:
RGB666/RGB888 PWM1
R2
VPBE:
RGB666/RGB888 PWM2
B2
CLK_OUT0
CLK_OUT1
PinMux1:
PWM0
PinMux0:
RGB666/
PinMux0:
RGB888
PWM1:
PinMux1:
PWM1
GPIO:
GPIO[47]
PWM2:
PinMux0:
RGB666/
PinMux0:
RGB888
PinMux1:
PWM2
GPIO:
GPIO[48]
PinMux1:
CLK0
PinMux1:
CLK1
TIMER0:
TIM_IN
PinMux1:
TIM_IN
GPIO:
GPIO[50:51]
ATA:
ATA_CS0,
ATA_CS1
EMIFA:
EM_BA[1]
EMIFA:
EM_A[0]
EMAC:
(all pins, except
CRS)
(4)
EMAC:
CRS,
MDIO:
MDIO, MDCLK
ATA (CF):
DMACK,DMARQ
UART2:
UART_RXD2,
UART_TXD2
UART2:
UART_CTS2,
UART_RTS2
PinMux0:
ATAEN
EMIFA, GPIO, ATA
(CF)
EMIFA, ATA (CF),
GPIO
EMAC, GPIO3V
GPIO:
GPIO[52]
ATA (CF):
DA1
ATA (CF):
DA2
PinMux0:
AEAW[4:0],
Pins:
DAEAW[4:0]
PinMux0:
AEAW[4:0],
Pins
:DAEAW[4:0]
PinMux0:
EMACEN
PinMux0:
ATAEN
GPIO:
GPIO[53]
PinMux0:
ATAEN,
Pins:
BTSEL[1:0] = 10
GPIO:
GPIO3V[0:13]
EMAC, MDIO,
GPIO3V
GPIO:
GPIO3V[14:16]
PinMux0:
EMACEN
UART1, ATA (CF)
N/A
UART1:
TXD, RXD
PinMux0:
ATAEN
PinMux1:
UART1
UART2, VPFE
VPFE:
CI[7:6]/
CCD_DATA[15:14]
VPFE:
CI[5:4]/
CCD_DATA[13:12]
PinMux1:
UART2
UART2, VPFE
PinMux1:
UART2,
PinMux1:
U2FLO
After device reset, the PINMUX0 and PINMUX1 registers are software programmable to allow multiplexing
of shared device pins between peripherals, as given in the Terminal Functions section.
Section 3.6.4
,
Section 3.6.5
, and
Section 3.6.6
identify the register settings necessary to configure specific multiplexed
functions and show the primary (default) function after reset.
The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins
among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, and GPIO peripherals. The register
format is shown in
Figure 3-8
and bit field descriptions are given in
Table 3-17
. More details on the
PINMUX0 pin muxing fields are given in
Section 3.6.6
. A value of "1" enables the secondary or tertiary pin
function.
Device Configuration
71