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P
2.7
Terminal Functions
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
The terminal functions tables (
Table 2-9
through
Table 2-33
) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see the Device Configurations section of this data sheet.
Table 2-9. BOOT Terminal Functions
SIGNAL
IPD/
IPU
(2)
TYPE
(1)
DESCRIPTION
NAME
NO.
BOOT
These pins are multiplexed between ARM boot mode and the VPBE. At
reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to
determine the ARM boot configuration. See below for the boot modes set
by these inputs. See the Bootmode section for more details.
After reset, these are video encoder outputs COUT0 and COUT1, or
RGB666/888 Blue output data bits 3 and 4 B3/B4.
BTSEL1
BTSEL0
0
0
ARM ROM Boot (NAND) [default]
0
1
ARM EMIFA Boot (NOR)
1
0
Reserved
1
1
ARM ROM Boot (UART)
This pin is multiplexed between EMIFA and the VPBE. At reset, the input
state is sampled to set the EMIFA data bus width (EM_WIDTH). For an
8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data
bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output
data bit 5 B5.
This pin is multiplexed between DSP boot and the VPBE. At reset, the
input state is sampled to set the DSP boot source DSP_BT. The DSP is
booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when
DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data
bit 6 output B6.
COUT0/
B3/
BTSEL0
A16
I/O/Z
IPD
ARM Boot Mode
COUT1/
B4/
BTSEL1
B16
I/O/Z
IPD
COUT2/
B5/
EM_WIDTH
A17
I/O/Z
IPD
COUT3/
B6/
DSP_BT
B17
I/O/Z
IPD
YOUT0/
G5/
AEAW0
YOUT1/
G6/
AEAW1
YOUT2/
G7/
AEAW2
YOUT3/
R3/
AEAW3
YOUT4/
R4/
AEAW4
D15
I/O/Z
IPD
D16
I/O/Z
IPD
These pins are multiplexed between EMIFA and the VPBE. At reset, the
input states of AEAW[4:0] are sampled to set the EMIFA address bus
width. See the Peripheral Selection at Device Reset section for details.
After reset, these are video encoder outputs YOUT[0:4] or RGB666/888
Red and Green data bit outputs G5, G6, G7, R3, and R4.
D17
I/O/Z
IPD
D18
I/O/Z
IPD
E15
I/O/Z
IPD
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k
resistor should be used.)
Device Overview
29