![](http://datasheet.mmic.net.cn/370000/TMX320DM6446ZWT_datasheet_16742798/TMX320DM6446ZWT_68.png)
www.ti.com
P
3.6
Configurations After Reset
3.6.1
Switched Central Resource (SCR) Bus Priorities
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 3-14. GPIO and EMIFA Multiplexing (Part 3)
Pin Mux Register AEAW[4:0] Bit Settings
10000
10001
EM_BA[1]
EM_BA[1]
EM_A[0]
EM_A[0]
EM_A[1]
EM_A[1]
EM_A[2]
EM_A[2]
EM_A[3]
EM_A[3]
EM_A[4]
EM_A[4]
EM_A[5]
EM_A[5]
EM_A[6]
EM_A[6]
EM_A[7]
EM_A[7]
EM_A[8]
EM_A[8]
EM_A[9]
EM_A[9]
EM_A[10]
EM_A[10]
EM_A[11]
EM_A[11]
EM_A[12]
EM_A[12]
EM_A[13]
EM_A[13]
EM_A[14]
EM_A[14]
GPIO[16]
EM_A[15]
GPIO[15]
GPIO[15]
GPIO[14]
GPIO[14]
GPIO[13]
GPIO[13]
GPIO[12]
GPIO[12]
GPIO[11]
GPIO[11]
GPIO[10]
GPIO[10]
10010
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
10011
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
10100
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
GPIO[12]
GPIO[11]
GPIO[10]
10101
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
GPIO[11]
GPIO[10]
10110
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
GPIO[10]
Others
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_A[14]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
EM_A[21]
The following sections give the details on configuring the device after reset.
Prioritization within the switched central resource (SCR) is selected to be either fixed or dynamic. Dynamic
prioritization is based on the incoming epriority signals from each master. On DM6446, only the C64x+,
VPSS, and EDMA masters actually generate epriority values. For all other masters, the value is
programmed in the chip-level MSTPRI0/1 registers. The register bit fields and default priority levels for
DM6446 bus masters are shown in
Table 3-15
. The priority levels should be tuned to obtain the best
system performance for a particular application. Details on the MSTPRI0/1 registers are given in
Figure 3-6
and
Figure 3-7
.
Table 3-15. DM6446 Default Bus Master Priorities
Priority Bit Field
VPSSP
EDMATC0P
EDMATC1P
ARM_DMAP
ARM_CFGP
C64X+_DMAP
C64X+_CFGP
Bus Master
VPSS
EDMATC0
EDMATC1
ARM (DMA)
ARM (CFG)
C64X+ (DMA)
C64X+ (CFG)
Default Priority Level
0 (VPSS PCR Register)
0 (EDMACC QUEPRI Register)
0 (EDMACC QUEPRI Register)
1
1
7 (C64X+ MDMAARBE.PRI Register bit field)
1
68
Device Configuration