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TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
Table 2-23. VPFE Terminal Functions (continued)
SIGNAL
NAME
IPD/
IPU
(2)
TYPE
(1)
DESCRIPTION
NO.
This pin is CCDC input YI5 and it supports several modes. In 16-bit CCD AFE
mode, it is input CCD5.
In 16-bit YCbCr mode, it is input Y5.
In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the
lower 8-bit channel.
This pin is CCDC input YI4 and it supports several modes.
In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD4.
In 16-bit YCbCr mode, it is input Y4.
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the
lower 8-bit channel.
This pin is CCDC input YI3 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD3.
In 16-bit YCbCr mode, it is input Y3.
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the
lower 8-bit channel.
This pin is CCDC input YI2 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD2.
In 16-bit YCbCr mode, it is input Y2.
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the
lower 8-bit channel.
This pin is CCDC input YI1 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD1.
In 16-bit YCbCr mode, it is input Y1.
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the
lower 8-bit channel.
This pin is CCDC input YI0 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD0.
In 16-bit YCbCr mode, it is input Y0.
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the
lower 8-bit channel.
This pin is multiplexed between GPIO and the VPFE. In GPIO mode, it is GPIO
pin GPIO1.
In VPFE mode, it is the CCD Controller write enable input C_WE.
This pin is multiplexed between GPIO, the VPFE, and the VPBE. In GPIO mode, it
is GPIO pin GPIO4.
In VPBE mode, it is RGB888 Red data bit 0 output R0.
In VPFE mode, it is CCDC field identification bidirectional signal C_FIELD.
YI5/
CCD5
L16
I
IPD
YI4/
CCD4
L15
I
IPD
YI3/
CCD3
K19
I
IPD
YI2/
CCD2
K18
I
IPD
YI1/
CCD1
K17
I
IPD
YI0/
CCD0
K16
I
IPD
GPIO1/
C_WE
E13
I/O/Z
IPD
GPIO4/
R0/
C_FIELD
B14
I/O/Z
IPD
Table 2-24. VPBE Terminal Functions
SIGNAL
IPD/
IPU
(2)
TYPE
(1)
DESCRIPTION
NAME
NO.
VIDEO OUT (VPBE)
HSYNC
VSYNC
VCLK
VPBECLK
C17
C18
D19
C19
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
VPBE Horizontal Synch Output
VPBE Vertical Synch Output
VPBE Clock Output
VPBE Clock Input
These pins are multiplexed between ARM boot mode and the VPBE. At
reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to
determine the ARM boot configuration. See below for the boot modes set
by these inputs. See the Bootmode section for more details.
After reset, these are video encoder outputs COUT0 and COUT1, or
RGB666/888 Blue output data bits 3 and 4 B3/B4.
COUT0/
B3/
BTSEL0
A16
I/O/Z
IPD
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k
resistor should be used.)
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