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APPENDIX B INSTRUCTION SET LIST
User’s Manual U16890EJ1V0UD
853
(6/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
SUB
reg1,reg2
rrrrr001101RRRRR
GR[reg2]
←
GR[reg2]–GR[reg1]
1
1
1
×
×
×
×
SUBR
reg1,reg2
rrrrr001100RRRRR
GR[reg2]
←
GR[reg1]–GR[reg2]
1
1
1
×
×
×
×
SWITCH
reg1
00000000010RRRRR
adr
←
(PC+2) + (GR [reg1] logically shift left by 1)
PC
←
(PC+2) + (sign-extend
(Load-memory (adr,Halfword))
logically shift left by 1
5
5
5
SXB
reg1
00000000101RRRRR
GR[reg1]
←
sign-extend
(GR[reg1] (7 : 0))
1
1
1
SXH
reg1
00000000111RRRRR
GR[reg1]
←
sign-extend
(GR[reg1] (15 : 0))
1
1
1
TRAP
vector
00000111111iiiii
0000000100000000
EIPC
EIPSW
ECR.EICC
←
Interrupt code
PSW.EP
←
1
PSW.ID
←
1
PC
←
00000040H
←
PC+4 (Restored PC)
←
PSW
(when vector is 00H to 0FH)
00000050H
(when vector is 10H to 1FH)
3
3
3
TST
reg1,reg2
rrrrr001011RRRRR
result
←
GR[reg2] AND GR[reg1]
1
1
1
0
×
×
bit#3,disp16[reg1]
11bbb111110RRRRR
dddddddddddddddd
adr
←
GR[reg1]+sign-extend(disp16)
Z flag
←
Not (Load-memory-bit (adr,bit#3))
3
Note 3
3
Note 3
3
Note 3
×
TST1
reg2, [reg1]
rrrrr111111RRRRR
0000000011100110
adr
←
GR[reg1]
Z flag
←
Not (Load-memory-bit (adr,reg2))
3
Note 3
3
Note 3
3
Note 3
×
XOR
reg1,reg2
rrrrr001001RRRRR
GR[reg2]
←
GR[reg2] XOR GR[reg1]
1
1
1
0
×
×
XORI
imm16,reg1,reg2
rrrrr110101RRRRR
i i i i i i i i i i i i i i i i
GR[reg2]
←
GR[reg1] XOR zero-extend (imm16)
1
1
1
0
×
×
ZXB
reg1
00000000100RRRRR
GR[reg1]
←
zero-extend (GR[reg1] (7 : 0))
1
1
1
ZXH
reg1
00000000110RRRRR
GR[reg1]
←
zero-extend (GR[reg1] (15 : 0))
1
1
1
Notes 1.
dddddddd: Higher 8 bits of disp9.
2.
3 if there is an instruction that rewrites the contents of the PSW immediately before.
3.
If there is no wait state (3 + the number of read access wait states).
4.
n is the total number of list12 load registers. (According to the number of wait states. Also, if there
are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1)
5.
RRRRR: other than 00000.
6.
The lower halfword data only are valid.
7.
ddddddddddddddddddddd: The higher 21 bits of disp22.
8.
ddddddddddddddd: The higher 15 bits of disp16.
9.
According to the number of wait states (1 if there are no wait states).
10.
b: bit 0 of disp16.
11.
According to the number of wait states (2 if there are no wait states).