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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16890EJ1V0UD
214
(6) TMP0 option register 0 (TP0OPT0)
The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
0
TP0CCS1
0
1
TP0CCR1 register capture/compare selection
The TP0CCS1 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TP0OPT0
0
TP0CCS1TP0CCS0
0
0
0
TP0OVF
6
5
4
3
2
1
After reset: 00H R/W Address: FFFFF5A5H
TP0CCS0
0
1
TP0CCR0 register capture/compare selection
The TP0CCS0 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TP0OVF
Set (1)
Reset (0)
TMP0 overflow detection flag
The TP0OVF bit is reset when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
An interrupt request signal (INTTP0OV) is generated at the same time that the
TP0OVF bit is set to 1. The INTTP0OV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
The TP0OVF bit is not cleared even when the TP0OVF bit or the TP0OPT0
register are read when the TP0OVF bit = 1.
The TP0OVF bit can be both read and written, but the TP0OVF bit cannot be set
to 1 by software. Writing 1 has no influence on the operation of TMP0.
Overflow occurred
TP0OVF bit 0 written or TP0CTL0.TP0CE bit = 0
7
<0>
Cautions 1. Rewrite the TP0CCS1 and TP0CCS0 bits when the TP0CE
bit = 0. (The same value can be written when the TP0CE
bit = 1.) If rewriting was mistakenly performed, clear the
TP0CE bit to 0 and then set the bits again.
2. Be sure to clear bits 1 to 3, 6, and 7 to 0.