CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U16890EJ1V0UD
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(1) 16-bit timer counter 0n (TM0n)
The TM0n register is a 16-bit read-only register that counts count pulses. The counter is incremented in
synchronization with the rising edge of the input clock.
TM0n
(n = 0 to 3)
12
10
8
6
4
2
After reset: 0000H R Address: TM00 FFFFF600H, TM01 FFFFF610H,
TM02 FFFFF620H, TM03 FFFFF630H
14
0
13
11
9
7
5
3
15
1
The count value is reset to 0000H in the following cases.
<1> Reset
<2> If the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are cleared (0)
<3> If the valid edge of the TI0n0 pin is input in the mode in which clear & start occurs when inputting the
valid edge of the TI0n0 pin
<4> If the TM0n register and the CR0n0 register match each other in the mode in which clear & start occurs
on a match between the TM0n register and the CR0n0 register
<5> If the TOC0m.OSPT0m bit is set (1) in the one-shot pulse output mode
Remark
n = 0 to 3
m = 0, 1
(2) 16-bit timer capture/compare register 0n0 (CR0n0)
The CR0n0 register is a 16-bit register that combines capture register and compare register functions.
The CRC0n.CRC0n0 bit is used to set whether to use the CR0n0 register as a capture register or as a
compare register.
The CR0n0 register can be read or written in 16-bit units.
After reset, this register is cleared to 0000H.
CR0n0
(n = 0 to 3)
12
10
8
6
4
2
After reset: 0000H R/W Address: CR000 FFFFF602H, CR010 FFFFF612H,
CR020 FFFFF622H, CR030 FFFFF632H
14
0
13
11
9
7
5
3
15
1
(a) When using the CR0n0 register as a compare register
The value set to the CR0n0 register and the count value set to the TM0n register are always compared
and when these values match, an interrupt request signal (INTTM0n0) is generated. The values are
retained until rewritten.