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CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
User’s Manual U16890EJ1V0UD
501
(4) Divisor selection register n (BRGCAn)
This is an 8-bit register used to control the serial transfer speed (divisor of CSIA clock).
This register can be read or written in 8-bit units. However, when the CSISn.TSFn bit is 1, rewriting the
BRGCAn register is prohibited.
After reset, this register is set to 03H.
7
0
BRGCn1
0
0
1
1
BRGCn0
0
1
0
1
Selection of CSIAn serial clock (f
SCKA
division ratio)
BRGCAn
(n = 0, 1)
6
0
5
0
4
0
3
0
2
0
1
BRGCn1
0
BRGCn0
After reset: 03H R/W Address: BRGCA0 FFFFFD43H, BRGCA1 FFFFD53H
6 (f
SCKA
/6)
8 (f
SCKA
/8)
16 (f
SCKA
/16)
32 (f
SCKA
/32)
(5) Automatic data transfer address point specification register n (ADTPn)
This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data
transfer (CSIMAn.ATEn bit = 1).
This register can be read or written in 8-bit units. However, when the CSISn.TSFn bit is 1, rewriting the
ADTPn register is prohibited.
After reset, this register is cleared to 00H.
In the V850ES/KG1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated.
Example
When the ADTP0 register is set to 07H
8 bytes of FFFFFE00H to FFFFFE07H are transferred.
In repeat transfer mode (CSIMAn.ATMn bit = 1), transfer is performed repeatedly up to the address value
specified by ADTPn.
Example
When the ADTP0 register is set to 07H (repeat transfer mode)
Transfer is repeated as FFFFFE00H to FFFFFE07H, … .
7
0
ADTPn
(n = 0, 1)
6
0
5
0
4
ADTPn4
3
ADTPn3
2
ADTPn2
1
ADTPn1
0
ADTPn0
After reset: 00H R/W Address: ADTP0 FFFFFD44H, ADTP1 FFFFD54H
Caution Be sure to clear bits 5 to 7 to 0.