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APPENDIX B INSTRUCTION SET LIST
User’s Manual U16890EJ1V0UD
849
(2/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
DBTRAP
1111100001000000 DBPC
←
PC+2 (restored PC)
DBPSW
←
PSW
PSW.NP
←
1
PSW.EP
←
1
PSW.ID
←
1
PC
←
00000060H
3
3
3
DI
0000011111100000
0000000101100000
PSW.ID
←
1
1
1
1
imm5,list12
0000011001iiiiiL
LLLLLLLLLLL00000
sp
←
sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]
←
Load-memory(sp,Word)
sp
←
sp+4
repeat 2 steps above until all regs in list12 is loaded
n+1
Note 4
n+1
Note 4
n+1
Note 4
DISPOSE
imm5,list12,[reg1]
0000011001iiiiiL
LLLLLLLLLLLRRRRR
Note 5
sp
←
sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]
←
Load-memory(sp,Word)
sp
←
sp+4
repeat 2 steps above until all regs in list12 is loaded
PC
←
GR[reg1]
n+3
Note 4
n+3
Note 4
n+3
Note 4
DIV
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01011000000
GR[reg2]
←
GR[reg2]÷GR[reg1]
GR[reg3]
←
GR[reg2]%GR[reg1]
35 35 35
×
×
×
reg1,reg2
rrrrr000010RRRRR
GR[reg2]
←
GR[reg2]÷GR[reg1]
Note 6
35 35 35
×
×
×
DIVH
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01010000000
GR[reg2]
←
GR[reg2]÷GR[reg1]
GR[reg3]
←
GR[reg2]%GR[reg1]
Note 6
35 35 35
×
×
×
DIVHU
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01010000010
GR[reg2]
←
GR[reg2]÷GR[reg1]
GR[reg3]
←
GR[reg2]%GR[reg1]
Note 6
34 34 34
×
×
×
DIVU
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01011000010
GR[reg2]
←
GR[reg2]÷GR[reg1]
GR[reg3]
←
GR[reg2]%GR[reg1]
34 34 34
×
×
×
EI
1000011111100000
0000000101100000
PSW.ID
←
0
1
1
1
HALT
0000011111100000
0000000100100000
Stop
1
1
1
HSW
reg2,reg3
rrrrr11111100000
wwwww01101000100
GR[reg3]
←
GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
1
1
1
×
0
×
×
JARL
disp22,reg2
rrrrr11110dddddd
ddddddddddddddd0
Note 7
GR[reg2]
←
PC+4
PC
←
PC+sign-extend(disp22)
2
2
2
JMP
[reg1]
00000000011RRRRR
PC
←
GR[reg1]
3
3
3
JR
disp22
0000011110dddddd
ddddddddddddddd0
Note 7
PC
←
PC+sign-extend(disp22)
2
2
2
LD.B
disp16[reg1],reg2
rrrrr111000RRRRR
dddddddddddddddd
adr
←
GR[reg1]+sign-extend(disp16)
GR[reg2]
←
sign-extend(Load-memory(adr,Byte))
1
1
Note
11
LD.BU
disp16[reg1],reg2
rrrrr11110bRRRRR
dddddddddddddd1
Notes 8, 10
adr
←
GR[reg1]+sign-extend(disp16)
GR[reg2]
←
zero-extend(Load-memory(adr,Byte))
1
1
Note
11