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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U16890EJ1V0UD
301
7
0
Operation stop
(TM0n cleared to 0)
Free-running timer
mode
Clear & start with
valid edge of TI0n0
Clear & start upon
match of TM0n and
CR0n0
Unchanged
Match of TM0n and
CR0n0 or match of
TM0n and CR0n1
Match of TM0n and
CR0n0 or match of
TM0n and CR0n1
Not generated
Generated upon
match of TM0n and
CR0n0 and match
of TM0n and CR0n1
TMC0n3
0
0
1
1
Selection of
operation mode
and clear mode
Selection of TO0n
output inverse timing
(n = 0 to 3)
6
0
5
0
4
0
3
TMC0n3
2
TMC0n2
1
TMC0n1
Note
<0>
OVF0n
TMC0n2
0
1
0
1
TMC0n1
Note
0
0
0
0
After reset: 00H R/W Address: TMC00 FFFFF606H, TMC01 FFFFF616H,
TMC02 FFFFF626H, TMC03 FFFFF636H
No overflow
Overflow
OVF0n
0
1
Detection of overflow of 16-bit timer register 0n
TMC0n
Generation of
interrupt
Other than above
Setting prohibited
Note
Be sure to clear the TMC0n1 bit to 0.
Cautions 1. Write to bits other than the OVF0n flag after stopping the timer operation.
2. The valid edge of the TI0n0 pin is set by the PRM0n register.
3. When the mode in which the timer is cleared and started upon match of TM0n and
CR0n0 is selected, the setting value of CR0n0 is FFFFH, and when the value of TM0n
changes from FFFFH to 0000H, the OVF0n flag is set to 1.
Remark
TO0n:
Output pin of 16-bit timer/event counter 0n
TI0n0: Input pin of 16-bit timer/event counter 0n
TM0n: 16-bit timer counter 0n
CR0n0: 16-bit timer capture/compare register 0n0
CR0n1: 16-bit timer capture/compare register 0n1
The following shows the I/O configuration of each channel and the selection of the TO0n output inversion timing
(setting of the TMC0n1 bit).
Table 8-5. I/O Configuration of Each Channel
Channel
Output Pin
Input Pin
I/O Pin
Setting of TMC0n1 Bit
TM00
TI001
TI000/TO00
Always clear to 0.
TM01
TI011
TI010/TO01
Always clear to 0.
TM02
TI021
TI020/TO02
0 (read only)
TM03
TI031
TI030/TO03
0 (read only)