![](http://datasheet.mmic.net.cn/370000/UPD70F3214HGC-8EU_datasheet_16743828/UPD70F3214HGC-8EU_322.png)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U16890EJ1V0UD
322
(3) Pulse width measurement with free-running timer operation and two capture registers
When 16-bit timer/event counter 0n is used in the free-running timer mode (refer to
Figure 8-14
), the pulse
width of the signal input to the TI0n0 pin can be measured.
When the edge specified by the PRM0n.ESn00 and PRM0n.ESn01 bits is input to the TI0n0 pin, the value of
the TM0n register is loaded to the CR0n1 register and an external interrupt request signal (INTTM0n1) is
generated.
The value of the TM0n register is also loaded to the CR0n0 register when an edge inverse to the one that
triggers capturing to the CR0n1 register is input.
The valid edge of the TI0n0 pin is detected through sampling at a count clock cycle selected with the PRM0n
register, and the capture operation is not performed until the valid edge is detected twice. As a result, noise
with a short pulse width can be eliminated.
Figure 8-14. Control Register Settings for Pulse Width Measurement
with Free-Running Timer Operation and Two Capture Registers
(with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
0
TMC0n
0
0
0
0
1
0
0
TMC0n3 TMC0n2 TMC0n1
OVF0n
Free-running timer mode
(b) Capture/compare control register 0n (CRC0n)
0
CRC0n
0
0
0
0
1
1
1
CRC0n2 CRC0n1 CRC0n0
CR0n0 used as capture register
Captures to CR0n0 at edge
inverse to valid edge of TI0n0 pin
CR0n1 used as capture register
(c) Prescaler mode register 0n (PRM0n)
0/1
0/1
0
1
0
3
PRM0n
2
PRM0n1
PRM0n0
ESn11
ESn10
ESn01
ESn00
Selects count clock
(Setting to 11 is prohibited.)
Specifies rising edge of
pulse width detection
Setting invalid
(Setting to 10 is prohibited.)
0
0/1
0/1
Remark
n = 0 to 3