69
Agere Systems Inc.
Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
7 Microprocessor Interface and Global Control and Status Registers
(continued)
Table 76. SMPR_MSRR, Block Software Reset Register (RW)
(continued)
Address
Bit
Name
Function
Reset
Default
0x0000
0x0000E
4
SMPR_XC_SWRS
XC Block Software Reset.
When this bit is set to 1, it
will create a software reset for the cross connect block.
This reset has the same effect as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All inter-
nal data path state machines within the block are also
reset.
M13 Block Software Reset.
When this bit is set to 1, it
will create a software reset for the M13 multiplexer/
demultiplexer block. This reset has the same effect as
the hardware reset and chip-level software reset.
3
SMPR_M13_SWRS
All microprocessor registers within the block are reset to
their default states. All internal data path state machines
within the block are also reset.
VTMPR Block Software Reset.
When this bit is set to 1,
it will create a software reset for the VTMPR block. This
reset has the same effect as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All inter-
nal data path state machines within the block are also
reset.
SMPR_SPEMPR_SWRS
SPEMPR Block Software Reset.
When this bit is set
to 1, it will create a software reset for the SPEMPR block.
This reset has the same effect as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All inter-
nal data path state machines within the block are also
reset.
SMPR_TMUX_SWRS
TMUX Block Software Reset.
When this bit is set to 1, it
will create a software reset for the TMUX block. This
reset has the same effect as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All inter-
nal data path state machines within the block are also
reset.
2
SMPR_VTMPR_SWRS
1
0