Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
121
Agere Systems Inc.
8 TMUX Registers
(continued)
Table 135. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO)
Table 136. TMUX_B3ECNT[1
—
3], Receive B3 Error Counts (RO)
Address
Bit
Name
Function
Reset
Default
0x000
0x00000
0x40067
0x40067
—
0x40068
15:2
1:0
RSVD
Reserved.
Receive High-Speed B2 Error Count.
Counts the
number of B2 errors in the received STS-3/STM-1
(AU-4) frame. This counter can either count actual
BIP errors or block errors; see TMUX_BITBLKB2
(
Table 105 on page 97
). This counter holds at its
maximum value or rolls over depending on the value
of SMPR_SAT_ROLLOVER, and transfers its internal
count to a holding register when SMPR_PMRESET
transitions from a logic 0 to 1.
15:0
TMUX_B2ECNT[17:16]
—
TMUX_B2ECNT[15:0]
Address
Bit
Name
Function
Reset
Default
0x0000
0x40069
15:0
TMUX_B3ECNT1[15:0]
Receive High-Speed B3 Error Count for Port 1.
Counts
the number of B3 errors in the receive STS-3/STM-1
(AU-4) frame for port 1. Only counter value 1 is valid in
AU-4 mode. This counter can either count actual BIP errors
or block errors; see TMUX_BITBLKB3 (
Table 105 on
page 97
). This counter holds at its maximum value or rolls
over depending on the value of SMPR_SAT_ROLLOVER
(
Table 77 on page 70
), and transfers its internal count to a
holding register when SMPR_PMRESET (
Table 75 on
page 68
) transitions from a logic 0 to 1.
TMUX_B3ECNT2[15:0]
Receive High-Speed B3 Error Count for Port 2.
Counts
the number of B3 errors in the receive STS-3/STM-1
(AU-4) frame for port 2. Only counter value 1 is valid in
AU-4 mode. This counter can either count actual BIP errors
or block errors; see TMUX_BITBLKB3 (
Table 105 on
page 97
). This counter holds at its maximum value or rolls
over depending on the value of SMPR_SAT_ROLLOVER,
and transfers its internal count to a holding register when
SMPR_PMRESET
transitions from a logic 0 to 1.
TMUX_B3ECNT3[15:0]
Receive High-Speed B3 Error Count for Port 3.
Counts
the number of B3 errors in the receive STS-3/STM-1
(AU-4) frame for port 3. Only counter value 1 is valid in
AU-4 mode. This counter can either count actual BIP errors
or block errors; see TMUX_BITBLKB3 (
Table 105 on
page 97
). This counter holds at its maximum value or rolls
over depending on the value of SMPR_SAT_ROLLOVER,
and transfers its internal count to a holding register when
SMPR_PMRESET
transitions from a logic 0 to 1.
0x4006A
15:0
0x0000
0x4006B
15:0
0x0000