TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
528
Agere Systems Inc.
21 28-Channel Framer Block Functional Description
(continued)
I
Any channel can be programmed to run for any combination of bits for any one time slot of either odd or even (or
both) frame numbers of any link.
I
A local loopback is supported. (From transmit FIFO through the HDLC back to the receive FIFO.)
I
The PRM data is received from the framer performance monitoring block approximately once per second per
link. If the link is enabled to send PRM data, then the PRM packet will be sent as the next packet on that link. The
PRM packet contains data for the current and three previous seconds. The format of the PRM packet is shown in
Table 599 on page 514
.
Table 608. Performance Report Message Structure
In
Table 608
, the flags (octet 1 and 15) are normal HDLC flags (note that the CFLAGS bit must be programmed to
1 to force nonshared flags), SAPI = 001110, C/R is programmable, EA = 0 in octet 2 and 1 in octet 3, TEI =
0000000, control = 00000011. Octets 5 and 6 contain the most recent data received from the performance monitor
(except U1, U2, R = 0 always). Octets 7 and 8 contain the same data from the previous second. Octets 9 and 10
contain data from the second before that (antepenultimate second) and octets 11 and 12 contain data for the sec-
ond before that. The FCS is automatically generated by the HDLC.
The data normally received from the performance monitor will be initialized to all zeros.
Transmit HDLC data is loaded into the channel transmit FIFO (TFIFO) via the Tx HDLC channel data bits
FRM_HTDATA[7:0] (
Table 450 on page 312
). Multiframes can be placed in the Tx HDLC FIFO. In HDLC mode,
the final byte of each frame is marked by writing the Tx HDLC FRM_HTFUNC[1:0] (
Table 450
) bits to the appropri-
ate value. The transmit HDLC channel count register indicates how many additional bytes can be added to the Tx
HDLC FIFO. The transmitter empty (Tx HDLC FRM_HTTHRSH (
Table 448 on page 311
)) interrupt bit is set in the
HDLC interrupt status register when the TFIFO is below the number of bytes specified in the threshold registers.
A Tx HDLC FRM_HTDONE interrupt occurs for each HDLC frame completed.
In HDLC mode, a Tx HDLC FRM_HTUND (
Table 448 on page 311
) interrupt is generated if the transmitter under-
runs. There is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist.
Overrunning transmitter data is ignored, which results in missing data in the frame.
Octet Number
1
2
3
4
5
6
7
8
9
10
11
12
13—14
15
PRM B7
PRM B6
PRM B5
PRM B4
PRM B3
PRM B2
PRM B1
PRM B0
FLAG
SAPI
C/R
EA
EA
TEI
Control
G3
FE
G3
FE
G3
FE
G3
FE
LV
SE
LV
SE
LV
SE
LV
SE
G4
LB
G4
LB
G4
LB
G4
LB
U1
G1
U1
G1
U1
G1
U1
G1
U2
R
U2
R
U2
R
U2
R
G5
G2
G5
G2
G5
G2
G5
G2
SL
Nm
SL
Nm
SL
Nm
SL
Nm
G6
NI
G6
NI
G6
NI
G6
NI
FCS
FLAG