
Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
211
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
Table 244. M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO)
Table 245. M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO)
Table 246. M13_DS2DMX_LOCD_R, DS2 DeMUX Loss of Clock Delta (RO)
Table 247. M13_DS1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO)
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10017
15:7
6:0
RSVD
Reserved
.
M13_DS2_LB_DETD[7:1]
Delta Bits.
These individual delta bits are set as the result
of the corresponding state bits M13_DS2_LB_DET[7:1]
(
Table 256 on page 214
) transitioning either from 0 to 1 or
from 1 to 0. Delta bits can be programmed to be either
clear on read (COR) or clear on write (COW), and they are
not set to 1 again until the event reoccurs.
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10018
15:7
6:0
RSVD
Reserved
.
M13_DS2_RSV_RCVD[7:1]
Delta Bits.
These individual delta bits are set as the
result of the corresponding state bits
M13_DS2_RSV_RCV[7:1] (
Table 257 on page 214
)
transitioning either from 0 to 1 or from 1 to 0. Delta bits
can be programmed to be either clear on read (COR) or
clear on write (COW), and they are not set to 1 again
until the event reoccurs. (G.747).
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10019
15:7
6:0
RSVD
Reserved
.
M13_DS2DMX_LOCD[7:1]
Delta Bits.
These individual delta bits are set as the
result of the corresponding state bits
M13_DS2DMX_LOC[7:1] (
Table 258 on page 214
) tran-
sitioning either from 0 to 1 or from 1 to 0. Delta bits can
be programmed to be either clear on read (COR) or clear
on write (COW), and they are not set to 1 again until the
event reoccurs.
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x1001E
0x1001F
—
0x10021
0x1001E
0x1001F
0x10020
0x10021
15:4
15:8
RSVD
RSVD
Reserved
.
Reserved
.
3:0
7:0
7:0
7:0
M13_DS1_LOCD[28:25]
M13_DS1_LOCD[24:17]
M13_DS1_LOCD[16:9]
M13_DS1_LOCD[8:1]
Delta Bits.
These individual delta bits are set as the
result of the corresponding state bits
M13_DS1_LOC[28:1] (
Table 259 on page 214
) transi-
tioning either from 0 to 1 or from 1 to 0. Delta bits can
be programmed to be either clear on read (COR) or
clear on write (COW), and they are not set to 1 again
until the event reoccurs.
0x00